A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding
This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-know...
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description | This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs. |
doi_str_mv | 10.1109/ACSD.2012.29 |
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A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. 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Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs.</description><subject>Asynchronous circuits</subject><subject>Circuit faults</subject><subject>Delay</subject><subject>Delay-insensitivity</subject><subject>Encoding</subject><subject>Error correcting codes</subject><subject>Fault-tolerance</subject><subject>GALS</subject><subject>Integrated circuit interconnections</subject><subject>Metastability</subject><subject>Protocols</subject><subject>Receivers</subject><subject>Registers</subject><issn>1550-4808</issn><issn>2374-8567</issn><isbn>9781467316873</isbn><isbn>1467316873</isbn><isbn>9780769547091</isbn><isbn>0769547095</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjDtPwzAYAM1Loird2Fj8Bxw-v-0xSilUqgRqu1eOY5OgNEFxItR_3wqYbrjTIfRIIaMU7HNe7JYZA8oyZq_QwmoDWlkpNFh6jWaMa0GMVPrm11GhNKfKaH6LZlRKIMKAuUeLlL4AgFqlFbMztM7xti-nNOI8nTpfD33XTwmvuzEM0fmm-8Q7X4djwD_NWONVPw3ko3Yp4OXkWrJ1TYuLvrp0D-guujaFxT_naL962RdvZPP-ui7yDWksjMRX3HMjrDWljlRVwUOMFfOiFE7GwKwGqQxnRkkPrhQxWOdD1MFHw7nifI6e_rZNCOHwPTRHN5wOikkuLvYMTt5Q7Q</recordid><startdate>201206</startdate><enddate>201206</enddate><creator>Lechner, J.</creator><creator>Lampacher, M.</creator><creator>Polzer, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201206</creationdate><title>A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding</title><author>Lechner, J. ; Lampacher, M. ; Polzer, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-cd3c384998b7f16dec0ffd2c4b4a5fe297056832865c0ab4fe9acef7ecf833633</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Asynchronous circuits</topic><topic>Circuit faults</topic><topic>Delay</topic><topic>Delay-insensitivity</topic><topic>Encoding</topic><topic>Error correcting codes</topic><topic>Fault-tolerance</topic><topic>GALS</topic><topic>Integrated circuit interconnections</topic><topic>Metastability</topic><topic>Protocols</topic><topic>Receivers</topic><topic>Registers</topic><toplevel>online_resources</toplevel><creatorcontrib>Lechner, J.</creatorcontrib><creatorcontrib>Lampacher, M.</creatorcontrib><creatorcontrib>Polzer, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lechner, J.</au><au>Lampacher, M.</au><au>Polzer, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding</atitle><btitle>2012 12th International Conference on Application of Concurrency to System Design</btitle><stitle>acsd</stitle><date>2012-06</date><risdate>2012</risdate><spage>122</spage><epage>131</epage><pages>122-131</pages><issn>1550-4808</issn><eissn>2374-8567</eissn><isbn>9781467316873</isbn><isbn>1467316873</isbn><eisbn>9780769547091</eisbn><eisbn>0769547095</eisbn><coden>IEEPAD</coden><abstract>This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. 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identifier | ISSN: 1550-4808 |
ispartof | 2012 12th International Conference on Application of Concurrency to System Design, 2012, p.122-131 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Asynchronous circuits Circuit faults Delay Delay-insensitivity Encoding Error correcting codes Fault-tolerance GALS Integrated circuit interconnections Metastability Protocols Receivers Registers |
title | A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding |
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