Simulation challenges in designing high speed serial links
Signal speeds of high speed serial links double almost every generation and with these increasing speeds come a wide range of new modeling and simulation challenges. Modeling challenges involve making sure that models are passive, stable and causal. Frequency-domain models, such as scattering parame...
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creator | Chada, A. R. Mutnury, B. Wallace, D. Winterberg, D. Minchuan Wang Scogna, A. C. |
description | Signal speeds of high speed serial links double almost every generation and with these increasing speeds come a wide range of new modeling and simulation challenges. Modeling challenges involve making sure that models are passive, stable and causal. Frequency-domain models, such as scattering parameter models that have measurement noise or limited bandwidth or incorrectly performed interpolation or extrapolation operations, may exhibit non-causality and non-passivity in time domain. Simulating millions of bits in timedomain to measure the interface merit in terms of bit error rate (BER) is CPU and memory intensive. This challenge has given way to new simulation algorithms and methodologies. The challenge here is that no two simulation approaches result in the same answer. The difference between approaches is aggravated at high frequencies and with inclusion of effects like crosstalk and transmitter and receiver equalization. In this paper, the results from various simulation approaches are contrasted against each other and also against measurements to understand their inherent assumptions along with their impact in designing high speed SerDes. |
doi_str_mv | 10.1109/ECTC.2012.6248821 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6248821</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6248821</ieee_id><sourcerecordid>6248821</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-4ad63eee007151c81e1e18b0f7e2876d51db4fab5f8e05a4d0783c3a19f500963</originalsourceid><addsrcrecordid>eNo1UMtOwzAQNC-JUPIBiIt_IMFrxy9uKCoPqRIHyrlykk1icE1VlwN_jyXKzmEOM5oZLSE3wGoAZu-W7bqtOQNeK94Yw-GEXEGjtACrGnFKCi60rqTm6oyUVpt_TdlzUjCpbCUlE5ekTOmD5csOEKog929--x3cwX9F2s8uBIwTJuojHTD5Kfo40dlPM007xIEm3HsXaPDxM12Ti9GFhOWRF-T9cblun6vV69NL-7CqPGh5qBo3KIGIuRMk9AYww3Rs1MiNVoOEoWtG18nRIJOuGfI20QsHdpSMWSUW5PYv1-eUzW7vt27_szm-QfwCCA1L8g</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Simulation challenges in designing high speed serial links</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Chada, A. R. ; Mutnury, B. ; Wallace, D. ; Winterberg, D. ; Minchuan Wang ; Scogna, A. C.</creator><creatorcontrib>Chada, A. R. ; Mutnury, B. ; Wallace, D. ; Winterberg, D. ; Minchuan Wang ; Scogna, A. C.</creatorcontrib><description>Signal speeds of high speed serial links double almost every generation and with these increasing speeds come a wide range of new modeling and simulation challenges. Modeling challenges involve making sure that models are passive, stable and causal. Frequency-domain models, such as scattering parameter models that have measurement noise or limited bandwidth or incorrectly performed interpolation or extrapolation operations, may exhibit non-causality and non-passivity in time domain. Simulating millions of bits in timedomain to measure the interface merit in terms of bit error rate (BER) is CPU and memory intensive. This challenge has given way to new simulation algorithms and methodologies. The challenge here is that no two simulation approaches result in the same answer. The difference between approaches is aggravated at high frequencies and with inclusion of effects like crosstalk and transmitter and receiver equalization. In this paper, the results from various simulation approaches are contrasted against each other and also against measurements to understand their inherent assumptions along with their impact in designing high speed SerDes.</description><identifier>ISSN: 0569-5503</identifier><identifier>ISBN: 9781467319669</identifier><identifier>ISBN: 146731966X</identifier><identifier>EISSN: 2377-5726</identifier><identifier>EISBN: 1467319643</identifier><identifier>EISBN: 9781467319652</identifier><identifier>EISBN: 1467319651</identifier><identifier>EISBN: 9781467319645</identifier><identifier>DOI: 10.1109/ECTC.2012.6248821</identifier><language>eng</language><publisher>IEEE</publisher><subject>bit error rate ; causality ; Convolution ; Crosstalk ; Data models ; Integrated circuit modeling ; interconnect ; Mathematical model ; passivity ; peak-distortion analysis ; Scattering parameters ; serial link ; statistical approaches ; Time domain analysis</subject><ispartof>2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.153-159</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6248821$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6248821$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chada, A. R.</creatorcontrib><creatorcontrib>Mutnury, B.</creatorcontrib><creatorcontrib>Wallace, D.</creatorcontrib><creatorcontrib>Winterberg, D.</creatorcontrib><creatorcontrib>Minchuan Wang</creatorcontrib><creatorcontrib>Scogna, A. C.</creatorcontrib><title>Simulation challenges in designing high speed serial links</title><title>2012 IEEE 62nd Electronic Components and Technology Conference</title><addtitle>ECTC</addtitle><description>Signal speeds of high speed serial links double almost every generation and with these increasing speeds come a wide range of new modeling and simulation challenges. Modeling challenges involve making sure that models are passive, stable and causal. Frequency-domain models, such as scattering parameter models that have measurement noise or limited bandwidth or incorrectly performed interpolation or extrapolation operations, may exhibit non-causality and non-passivity in time domain. Simulating millions of bits in timedomain to measure the interface merit in terms of bit error rate (BER) is CPU and memory intensive. This challenge has given way to new simulation algorithms and methodologies. The challenge here is that no two simulation approaches result in the same answer. The difference between approaches is aggravated at high frequencies and with inclusion of effects like crosstalk and transmitter and receiver equalization. In this paper, the results from various simulation approaches are contrasted against each other and also against measurements to understand their inherent assumptions along with their impact in designing high speed SerDes.</description><subject>bit error rate</subject><subject>causality</subject><subject>Convolution</subject><subject>Crosstalk</subject><subject>Data models</subject><subject>Integrated circuit modeling</subject><subject>interconnect</subject><subject>Mathematical model</subject><subject>passivity</subject><subject>peak-distortion analysis</subject><subject>Scattering parameters</subject><subject>serial link</subject><subject>statistical approaches</subject><subject>Time domain analysis</subject><issn>0569-5503</issn><issn>2377-5726</issn><isbn>9781467319669</isbn><isbn>146731966X</isbn><isbn>1467319643</isbn><isbn>9781467319652</isbn><isbn>1467319651</isbn><isbn>9781467319645</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UMtOwzAQNC-JUPIBiIt_IMFrxy9uKCoPqRIHyrlykk1icE1VlwN_jyXKzmEOM5oZLSE3wGoAZu-W7bqtOQNeK94Yw-GEXEGjtACrGnFKCi60rqTm6oyUVpt_TdlzUjCpbCUlE5ekTOmD5csOEKog929--x3cwX9F2s8uBIwTJuojHTD5Kfo40dlPM007xIEm3HsXaPDxM12Ti9GFhOWRF-T9cblun6vV69NL-7CqPGh5qBo3KIGIuRMk9AYww3Rs1MiNVoOEoWtG18nRIJOuGfI20QsHdpSMWSUW5PYv1-eUzW7vt27_szm-QfwCCA1L8g</recordid><startdate>201205</startdate><enddate>201205</enddate><creator>Chada, A. R.</creator><creator>Mutnury, B.</creator><creator>Wallace, D.</creator><creator>Winterberg, D.</creator><creator>Minchuan Wang</creator><creator>Scogna, A. C.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201205</creationdate><title>Simulation challenges in designing high speed serial links</title><author>Chada, A. R. ; Mutnury, B. ; Wallace, D. ; Winterberg, D. ; Minchuan Wang ; Scogna, A. C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-4ad63eee007151c81e1e18b0f7e2876d51db4fab5f8e05a4d0783c3a19f500963</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>bit error rate</topic><topic>causality</topic><topic>Convolution</topic><topic>Crosstalk</topic><topic>Data models</topic><topic>Integrated circuit modeling</topic><topic>interconnect</topic><topic>Mathematical model</topic><topic>passivity</topic><topic>peak-distortion analysis</topic><topic>Scattering parameters</topic><topic>serial link</topic><topic>statistical approaches</topic><topic>Time domain analysis</topic><toplevel>online_resources</toplevel><creatorcontrib>Chada, A. R.</creatorcontrib><creatorcontrib>Mutnury, B.</creatorcontrib><creatorcontrib>Wallace, D.</creatorcontrib><creatorcontrib>Winterberg, D.</creatorcontrib><creatorcontrib>Minchuan Wang</creatorcontrib><creatorcontrib>Scogna, A. C.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chada, A. R.</au><au>Mutnury, B.</au><au>Wallace, D.</au><au>Winterberg, D.</au><au>Minchuan Wang</au><au>Scogna, A. C.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Simulation challenges in designing high speed serial links</atitle><btitle>2012 IEEE 62nd Electronic Components and Technology Conference</btitle><stitle>ECTC</stitle><date>2012-05</date><risdate>2012</risdate><spage>153</spage><epage>159</epage><pages>153-159</pages><issn>0569-5503</issn><eissn>2377-5726</eissn><isbn>9781467319669</isbn><isbn>146731966X</isbn><eisbn>1467319643</eisbn><eisbn>9781467319652</eisbn><eisbn>1467319651</eisbn><eisbn>9781467319645</eisbn><abstract>Signal speeds of high speed serial links double almost every generation and with these increasing speeds come a wide range of new modeling and simulation challenges. Modeling challenges involve making sure that models are passive, stable and causal. Frequency-domain models, such as scattering parameter models that have measurement noise or limited bandwidth or incorrectly performed interpolation or extrapolation operations, may exhibit non-causality and non-passivity in time domain. Simulating millions of bits in timedomain to measure the interface merit in terms of bit error rate (BER) is CPU and memory intensive. This challenge has given way to new simulation algorithms and methodologies. The challenge here is that no two simulation approaches result in the same answer. The difference between approaches is aggravated at high frequencies and with inclusion of effects like crosstalk and transmitter and receiver equalization. In this paper, the results from various simulation approaches are contrasted against each other and also against measurements to understand their inherent assumptions along with their impact in designing high speed SerDes.</abstract><pub>IEEE</pub><doi>10.1109/ECTC.2012.6248821</doi><tpages>7</tpages></addata></record> |
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subjects | bit error rate causality Convolution Crosstalk Data models Integrated circuit modeling interconnect Mathematical model passivity peak-distortion analysis Scattering parameters serial link statistical approaches Time domain analysis |
title | Simulation challenges in designing high speed serial links |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T22%3A30%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Simulation%20challenges%20in%20designing%20high%20speed%20serial%20links&rft.btitle=2012%20IEEE%2062nd%20Electronic%20Components%20and%20Technology%20Conference&rft.au=Chada,%20A.%20R.&rft.date=2012-05&rft.spage=153&rft.epage=159&rft.pages=153-159&rft.issn=0569-5503&rft.eissn=2377-5726&rft.isbn=9781467319669&rft.isbn_list=146731966X&rft_id=info:doi/10.1109/ECTC.2012.6248821&rft_dat=%3Cieee_6IE%3E6248821%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1467319643&rft.eisbn_list=9781467319652&rft.eisbn_list=1467319651&rft.eisbn_list=9781467319645&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6248821&rfr_iscdi=true |