A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance

A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance

A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within te...

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Hauptverfasser: Yu-Huei Lee, Shen-Yu Peng, Wu, A. C-H, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS integrated circuits
Digital signal processing
Hybrid power systems
Pipelines
Power demand
Regulators
Voltage control
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creator Yu-Huei Lee
Shen-Yu Peng
Wu, A. C-H
Chao-Chang Chiu
Yao-Yi Yang
Ming-Hsin Huang
Ke-Horng Chen
Ying-Hsi Lin
Shih-Wei Wang
Ching-Yuan Yeh
Chen-Chih Huang
Chao-Cheng Lee
description A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within tens of nano-seconds. The SWR with the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation. The fabricated chip occupies 1.04mm 2 in 40nm CMOS.
doi_str_mv 10.1109/VLSIC.2012.6243848
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects CMOS integrated circuits
Digital signal processing
Hybrid power systems
Pipelines
Power demand
Regulators
Voltage control
title A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance
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