A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology

A 8-b 2-b/step asynchronous subranged SAR ADC is presented. It incorporates subranging technique to obtain fast reference settling for MSB conversion. The capacitive interpolation reduces number of NMOS switches and lowers matching requirement of a resistive DAC. The proposed timing scheme avoids th...

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Bibliographische Detailangaben

1. Verfasser:	Yuan-Ching Lien
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitors Clocks CMOS integrated circuits CMOS technology Preamplifiers Resistors Timing
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