A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS

1Mbit SRAM macro with adaptive leakage current reduction scheme is implemented in 28nm high-k metal gate CMOS technology. A current limiter that limits cell array leakage current at various process-voltage-temperature (PVT) corners is included in the proposed scheme. The leakage current is reduced b...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hsu, P. K., Yukit Tang, Tao, Derek, Ming-Chieh Huang, Min-Jer Wang, Wu, C. H., Lee, Q.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arrays Current limiters Current measurement Leakage current Random access memory Temperature measurement Transistors
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!