High-aspect ratio through silicon via (TSV) technology

High-aspect ratio through silicon via (TSV) technology

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vic...

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Hauptverfasser: Chang, H. B., Chen, H. Y., Kuo, P. C., Chien, C. H., Liao, E. B., Lin, T. C., Wei, T. S., Lin, Y. C., Chen, Y. H., Yang, K. F., Teng, H. A., Tsai, W. C., Tseng, Y. C., Chen, S. Y., Hsieh, C. C., Chen, M. F., Liu, Y. H., Wu, T. J., Hou, S. Y., Chiou, W. C., Jeng, S. P., Yu, C. H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
MOSFET circuits
MOSFETs
Performance evaluation
Silicon
Strain
Stress
Through-silicon vias
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Zusammenfassung:The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.
ISSN:0743-1562
DOI:10.1109/VLSIT.2012.6242517