Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation
We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel "local ground plan...
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| creator | Yamamoto, Y. Makiyama, H. Tsunomura, T. Iwamatsu, T. Oda, H. Sugii, N. Yamaguchi, Y. Mizutani, T. Hiramoto, T. |
| description | We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel "local ground plane (LGP)" structure that significantly improves short-channel effect (V th roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme. |
| doi_str_mv | 10.1109/VLSIT.2012.6242485 |
| format | Conference Proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0743-1562 |
| ispartof | 2012 Symposium on VLSI Technology (VLSIT), 2012, p.109-110 |
| issn | 0743-1562 |
| language | eng ; jpn |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Hafnium High K dielectric materials Logic gates Random access memory Silicon Transistors Very large scale integration |
| title | Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation |
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