Concurrent Generation of Concurrent Programs for Post-Silicon Validation

The continuing trend toward increased parallelism in processor design can be seen in both the growing number of processor cores per system and in on-core hardware mechanisms that assist parallelism, such as multithreading and cache hierarchies. This complexity exacerbates the problem of ensuring the...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2012-08, Vol.31 (8), p.1297-1302
Hauptverfasser:	Adir, A., Nahir, A., Ziv, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Functional verification Generators Hardware Instruction sets Integrated circuit interconnections Integrated circuit modeling multiprocessor verification multithreading post-silicon validation Silicon stimuli generation Timing
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