Concurrent Generation of Concurrent Programs for Post-Silicon Validation

The continuing trend toward increased parallelism in processor design can be seen in both the growing number of processor cores per system and in on-core hardware mechanisms that assist parallelism, such as multithreading and cache hierarchies. This complexity exacerbates the problem of ensuring the...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2012-08, Vol.31 (8), p.1297-1302
Hauptverfasser: Adir, A., Nahir, A., Ziv, A.
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creator Adir, A.
Nahir, A.
Ziv, A.
description The continuing trend toward increased parallelism in processor design can be seen in both the growing number of processor cores per system and in on-core hardware mechanisms that assist parallelism, such as multithreading and cache hierarchies. This complexity exacerbates the problem of ensuring the functional correctness of such hardware systems. The growing importance of post-silicon validation is leading to an emerging type of parallel application, namely, the hardware exerciser. We describe a method for exercising parallel hardware by generating pseudorandom concurrent test programs. The test generation is carried out on the tested parallel platform and thus the generator itself is also a concurrent program. We describe the challenges associated with this technology and the approach used by the Threadmill hardware exerciser, a tool developed for the post-silicon validation of the IBM POWER7 processor.
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subjects Functional verification
Generators
Hardware
Instruction sets
Integrated circuit interconnections
Integrated circuit modeling
multiprocessor verification
multithreading
post-silicon validation
Silicon
stimuli generation
Timing
title Concurrent Generation of Concurrent Programs for Post-Silicon Validation
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