3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

The 3D IC stacking technology with Through Silicon via (TSV) approach promises lower cost, smaller footprint and higher performance for heterogeneous system integration. 3D integration technology needs key components to be enabled: Like TSV technology, Wafer thinning, thin wafer carrier and handling...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Guo, W., Van Der Plas, G., Ivankovic, A., Eneman, G., Cherman, V., De Wachter, B., Mercha, A., Gonzalez, M., Civale, Y., Redolfi, A., Buisson, T., Jourdan, A., Vandevelde, B., Rebibis, K. J., De Wolf, I., La Manna, A., Beyer, G., Beyne, E., Swinnen, B.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	3D IC CMOS keep out zone mechnical stress Performance evaluation Proximity effects Silicon Stress Through-silicon vias TSV μBump
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