VHDL simulation acceleration using specialized functions

We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepar...

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Hauptverfasser:	Taekyoon Ahn, Kiyoung Choi
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Acceleration Analytical models Circuit simulation Degradation Design methodology Design optimization Discrete event simulation Hardware design languages Libraries
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container_end_page	1687 vol.3
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creator	Taekyoon Ahn Kiyoung Choi
description	We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for each possible case. When a design is compiled and the simulation code is generated, we select functions that best fit with the design. With this approach and with several other optimization techniques, we obtained about twofold speedup.
doi_str_mv	10.1109/ISCAS.1997.621458
format	Conference Proceeding
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In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for each possible case. When a design is compiled and the simulation code is generated, we select functions that best fit with the design. With this approach and with several other optimization techniques, we obtained about twofold speedup.</description><subject>Acceleration</subject><subject>Analytical models</subject><subject>Circuit simulation</subject><subject>Degradation</subject><subject>Design methodology</subject><subject>Design optimization</subject><subject>Discrete event simulation</subject><subject>Hardware design languages</subject><subject>Libraries</subject><isbn>9780780335837</isbn><isbn>078033583X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1997</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpjYJA0NNAzNDSw1PcMdnYM1jO0tDTXMzMyNDG1YGbgtTS3MAAiY2NTC2NzDgbe4uIsAyAwMTWxNDXiZLAI83DxUSjOzC3NSSzJzM9TSExOTs1JLYJwSosz89IVigtSkzMTczKrUlMU0krzkkFSxTwMrGmJOcWpvFCam0HKzTXE2UM3MzU1Nb6gKDM3sagyHuIMY7ySABRWNrU</recordid><startdate>1997</startdate><enddate>1997</enddate><creator>Taekyoon Ahn</creator><creator>Kiyoung Choi</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1997</creationdate><title>VHDL simulation acceleration using specialized functions</title><author>Taekyoon Ahn ; Kiyoung Choi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_6214583</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Acceleration</topic><topic>Analytical models</topic><topic>Circuit simulation</topic><topic>Degradation</topic><topic>Design methodology</topic><topic>Design optimization</topic><topic>Discrete event simulation</topic><topic>Hardware design languages</topic><topic>Libraries</topic><toplevel>online_resources</toplevel><creatorcontrib>Taekyoon Ahn</creatorcontrib><creatorcontrib>Kiyoung Choi</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Taekyoon Ahn</au><au>Kiyoung Choi</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>VHDL simulation acceleration using specialized functions</atitle><btitle>1997 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>1997</date><risdate>1997</risdate><volume>3</volume><spage>1684</spage><epage>1687 vol.3</epage><pages>1684-1687 vol.3</pages><isbn>9780780335837</isbn><isbn>078033583X</isbn><abstract>We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for each possible case. When a design is compiled and the simulation code is generated, we select functions that best fit with the design. With this approach and with several other optimization techniques, we obtained about twofold speedup.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.1997.621458</doi></addata></record>
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subjects	Acceleration Analytical models Circuit simulation Degradation Design methodology Design optimization Discrete event simulation Hardware design languages Libraries
title	VHDL simulation acceleration using specialized functions
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