Minimal logic re-synthesis for engineering change
We propose an iterative solution to the problem of logic re-synthesis; we begin with a small region for re-synthesis (selected using some criteria), and iteratively expand that region until a solution is obtained. At each stage, we test if this resynthesizing this region alone can realize the new sp...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 1599 vol.3 |
---|---|
container_issue | |
container_start_page | 1596 |
container_title | |
container_volume | 3 |
creator | Swamy, G. Rajamani, S. Lennard, C. Brayton, R.K. |
description | We propose an iterative solution to the problem of logic re-synthesis; we begin with a small region for re-synthesis (selected using some criteria), and iteratively expand that region until a solution is obtained. At each stage, we test if this resynthesizing this region alone can realize the new specification. As a second pass, we trim the region iteratively, so that it becomes minimal in the sense that no subset of the current region can realize the change in functionality. However, not all minimal regions are equivalent in terms of their power, area or delay optimality. To compare two different minimal re-synthesis regions, we use a heuristic evaluation criteria for the acceptability of regions for re-synthesis called sensitivity. We compute the sensitivity (or acceptability for resynthesis) for power. This sensitivity criteria is used to pick nodes in the iterative scheme. An iterative algorithm is given for incremental synthesis that begins with an empty re-synthesis region, and iteratively picks nodes from the rest of the network to add to the region (in order of their sensitivity). |
doi_str_mv | 10.1109/ISCAS.1997.621436 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_621436</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>621436</ieee_id><sourcerecordid>621436</sourcerecordid><originalsourceid>FETCH-ieee_primary_6214363</originalsourceid><addsrcrecordid>eNpjYJA0NNAzNDSw1PcMdnYM1jO0tDTXMzMyNDE2Y2bgtTS3MAAiY2NTC2NzDgbe4uIsAyAwMTWxNDXiZDD0zczLzE3MUcjJT89MVihK1S2uzCvJSC3OLFZIyy9SSM1Lz8xLTS3KzEtXSM5IzEtP5WFgTUvMKU7lhdLcDFJuriHOHrqZqamp8QVFQNOKKuMh9hvjlQQAWvEztA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Minimal logic re-synthesis for engineering change</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Swamy, G. ; Rajamani, S. ; Lennard, C. ; Brayton, R.K.</creator><creatorcontrib>Swamy, G. ; Rajamani, S. ; Lennard, C. ; Brayton, R.K.</creatorcontrib><description>We propose an iterative solution to the problem of logic re-synthesis; we begin with a small region for re-synthesis (selected using some criteria), and iteratively expand that region until a solution is obtained. At each stage, we test if this resynthesizing this region alone can realize the new specification. As a second pass, we trim the region iteratively, so that it becomes minimal in the sense that no subset of the current region can realize the change in functionality. However, not all minimal regions are equivalent in terms of their power, area or delay optimality. To compare two different minimal re-synthesis regions, we use a heuristic evaluation criteria for the acceptability of regions for re-synthesis called sensitivity. We compute the sensitivity (or acceptability for resynthesis) for power. This sensitivity criteria is used to pick nodes in the iterative scheme. An iterative algorithm is given for incremental synthesis that begins with an empty re-synthesis region, and iteratively picks nodes from the rest of the network to add to the region (in order of their sensitivity).</description><identifier>ISBN: 9780780335837</identifier><identifier>ISBN: 078033583X</identifier><identifier>DOI: 10.1109/ISCAS.1997.621436</identifier><language>eng</language><publisher>IEEE</publisher><subject>Boolean functions ; Circuit synthesis ; Delay ; Logic circuits ; Logic design ; Logic gates ; Network synthesis ; Regions ; Sections ; Transfer functions</subject><ispartof>1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997, Vol.3, p.1596-1599 vol.3</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/621436$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/621436$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Swamy, G.</creatorcontrib><creatorcontrib>Rajamani, S.</creatorcontrib><creatorcontrib>Lennard, C.</creatorcontrib><creatorcontrib>Brayton, R.K.</creatorcontrib><title>Minimal logic re-synthesis for engineering change</title><title>1997 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>We propose an iterative solution to the problem of logic re-synthesis; we begin with a small region for re-synthesis (selected using some criteria), and iteratively expand that region until a solution is obtained. At each stage, we test if this resynthesizing this region alone can realize the new specification. As a second pass, we trim the region iteratively, so that it becomes minimal in the sense that no subset of the current region can realize the change in functionality. However, not all minimal regions are equivalent in terms of their power, area or delay optimality. To compare two different minimal re-synthesis regions, we use a heuristic evaluation criteria for the acceptability of regions for re-synthesis called sensitivity. We compute the sensitivity (or acceptability for resynthesis) for power. This sensitivity criteria is used to pick nodes in the iterative scheme. An iterative algorithm is given for incremental synthesis that begins with an empty re-synthesis region, and iteratively picks nodes from the rest of the network to add to the region (in order of their sensitivity).</description><subject>Boolean functions</subject><subject>Circuit synthesis</subject><subject>Delay</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>Logic gates</subject><subject>Network synthesis</subject><subject>Regions</subject><subject>Sections</subject><subject>Transfer functions</subject><isbn>9780780335837</isbn><isbn>078033583X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1997</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpjYJA0NNAzNDSw1PcMdnYM1jO0tDTXMzMyNDE2Y2bgtTS3MAAiY2NTC2NzDgbe4uIsAyAwMTWxNDXiZDD0zczLzE3MUcjJT89MVihK1S2uzCvJSC3OLFZIyy9SSM1Lz8xLTS3KzEtXSM5IzEtP5WFgTUvMKU7lhdLcDFJuriHOHrqZqamp8QVFQNOKKuMh9hvjlQQAWvEztA</recordid><startdate>1997</startdate><enddate>1997</enddate><creator>Swamy, G.</creator><creator>Rajamani, S.</creator><creator>Lennard, C.</creator><creator>Brayton, R.K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1997</creationdate><title>Minimal logic re-synthesis for engineering change</title><author>Swamy, G. ; Rajamani, S. ; Lennard, C. ; Brayton, R.K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_6214363</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Boolean functions</topic><topic>Circuit synthesis</topic><topic>Delay</topic><topic>Logic circuits</topic><topic>Logic design</topic><topic>Logic gates</topic><topic>Network synthesis</topic><topic>Regions</topic><topic>Sections</topic><topic>Transfer functions</topic><toplevel>online_resources</toplevel><creatorcontrib>Swamy, G.</creatorcontrib><creatorcontrib>Rajamani, S.</creatorcontrib><creatorcontrib>Lennard, C.</creatorcontrib><creatorcontrib>Brayton, R.K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Swamy, G.</au><au>Rajamani, S.</au><au>Lennard, C.</au><au>Brayton, R.K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Minimal logic re-synthesis for engineering change</atitle><btitle>1997 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>1997</date><risdate>1997</risdate><volume>3</volume><spage>1596</spage><epage>1599 vol.3</epage><pages>1596-1599 vol.3</pages><isbn>9780780335837</isbn><isbn>078033583X</isbn><abstract>We propose an iterative solution to the problem of logic re-synthesis; we begin with a small region for re-synthesis (selected using some criteria), and iteratively expand that region until a solution is obtained. At each stage, we test if this resynthesizing this region alone can realize the new specification. As a second pass, we trim the region iteratively, so that it becomes minimal in the sense that no subset of the current region can realize the change in functionality. However, not all minimal regions are equivalent in terms of their power, area or delay optimality. To compare two different minimal re-synthesis regions, we use a heuristic evaluation criteria for the acceptability of regions for re-synthesis called sensitivity. We compute the sensitivity (or acceptability for resynthesis) for power. This sensitivity criteria is used to pick nodes in the iterative scheme. An iterative algorithm is given for incremental synthesis that begins with an empty re-synthesis region, and iteratively picks nodes from the rest of the network to add to the region (in order of their sensitivity).</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.1997.621436</doi></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISBN: 9780780335837 |
ispartof | 1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997, Vol.3, p.1596-1599 vol.3 |
issn | |
language | eng |
recordid | cdi_ieee_primary_621436 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Boolean functions Circuit synthesis Delay Logic circuits Logic design Logic gates Network synthesis Regions Sections Transfer functions |
title | Minimal logic re-synthesis for engineering change |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T23%3A10%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Minimal%20logic%20re-synthesis%20for%20engineering%20change&rft.btitle=1997%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Swamy,%20G.&rft.date=1997&rft.volume=3&rft.spage=1596&rft.epage=1599%20vol.3&rft.pages=1596-1599%20vol.3&rft.isbn=9780780335837&rft.isbn_list=078033583X&rft_id=info:doi/10.1109/ISCAS.1997.621436&rft_dat=%3Cieee_6IE%3E621436%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=621436&rfr_iscdi=true |