An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V read ) and cell Inverter Trip voltage (V trip ) in SRAM cell array environment. Measured voltages are converted to frequency with Voltag...

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Hauptverfasser:	Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arrays Inverters Microprocessors Random access memory Voltage measurement Voltage-controlled oscillators
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