A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video
To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based ad...
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| Veröffentlicht in: | IEEE transactions on circuits and systems for video technology 2012-11, Vol.22 (11), p.1604-1610 |
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| container_issue | 11 |
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| container_title | IEEE transactions on circuits and systems for video technology |
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| creator | LIAO, Yuan-Hsin LI, Gwo-Long CHANG, Tian-Sheuan |
| description | To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54k gate counts under 90-nm CMOS technology. |
| doi_str_mv | 10.1109/TCSVT.2012.2202081 |
| format | Article |
| fullrecord | <record><control><sourceid>pascalfrancis_RIE</sourceid><recordid>TN_cdi_ieee_primary_6209405</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6209405</ieee_id><sourcerecordid>26625297</sourcerecordid><originalsourceid>FETCH-LOGICAL-c227t-928e18810a7ac9a7a08589a1be106b22e8c6b20d46cd24c02818a977e3af43213</originalsourceid><addsrcrecordid>eNo9kEFPwzAMhSMEEmPwB-CSC8d2sdu06XEUWBFFHOh64VBlqSsVFTolE2j8ejI27eJn6_lZ8sfYNYgQQGSzKn-rqxAFYIgoUCg4YROQUgV-lKe-FxIChSDP2YVzH0JArOJ0wt7nPFKSvxS_HKJQxvyZL_SGHL-nQW_5nR70l6GWVz9jUNI3DTyf12XubTO2ZHk3Wr4cNlbz4p4XISbxbF7nvO5bGi_ZWacHR1cHnbLl40OVF0H5unjK52VgENNNkKEiUAqETrXJfBFKqkzDikAkK0RSxoto48S0GBuBCpTO0pQi3cURQjRluL9r7Oicpa5Z2_5T220Dotnhaf7xNDs8zQGPD93uQ2vtjB466__s3TGJSYISs9Tv3ez3eiI62gmKLBYy-gPkFGgM</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video</title><source>IEEE Electronic Library (IEL)</source><creator>LIAO, Yuan-Hsin ; LI, Gwo-Long ; CHANG, Tian-Sheuan</creator><creatorcontrib>LIAO, Yuan-Hsin ; LI, Gwo-Long ; CHANG, Tian-Sheuan</creatorcontrib><description>To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54k gate counts under 90-nm CMOS technology.</description><identifier>ISSN: 1051-8215</identifier><identifier>EISSN: 1558-2205</identifier><identifier>DOI: 10.1109/TCSVT.2012.2202081</identifier><identifier>CODEN: ITCTEM</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit properties ; Coding, codes ; Context-adaptive variable length decoder (CAVLD) ; Decoding ; Delay ; Design. Technologies. Operation analysis. Testing ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Encoding ; Exact sciences and technology ; H.264 ; Image processing ; Information, signal and communications theory ; Integrated circuits ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal and communications theory ; Signal convertors ; Signal processing ; Telecommunications and information theory ; Throughput ; Video coding</subject><ispartof>IEEE transactions on circuits and systems for video technology, 2012-11, Vol.22 (11), p.1604-1610</ispartof><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c227t-928e18810a7ac9a7a08589a1be106b22e8c6b20d46cd24c02818a977e3af43213</citedby><cites>FETCH-LOGICAL-c227t-928e18810a7ac9a7a08589a1be106b22e8c6b20d46cd24c02818a977e3af43213</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6209405$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6209405$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=26625297$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>LIAO, Yuan-Hsin</creatorcontrib><creatorcontrib>LI, Gwo-Long</creatorcontrib><creatorcontrib>CHANG, Tian-Sheuan</creatorcontrib><title>A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video</title><title>IEEE transactions on circuits and systems for video technology</title><addtitle>TCSVT</addtitle><description>To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54k gate counts under 90-nm CMOS technology.</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Coding, codes</subject><subject>Context-adaptive variable length decoder (CAVLD)</subject><subject>Decoding</subject><subject>Delay</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Encoding</subject><subject>Exact sciences and technology</subject><subject>H.264</subject><subject>Image processing</subject><subject>Information, signal and communications theory</subject><subject>Integrated circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal and communications theory</subject><subject>Signal convertors</subject><subject>Signal processing</subject><subject>Telecommunications and information theory</subject><subject>Throughput</subject><subject>Video coding</subject><issn>1051-8215</issn><issn>1558-2205</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEFPwzAMhSMEEmPwB-CSC8d2sdu06XEUWBFFHOh64VBlqSsVFTolE2j8ejI27eJn6_lZ8sfYNYgQQGSzKn-rqxAFYIgoUCg4YROQUgV-lKe-FxIChSDP2YVzH0JArOJ0wt7nPFKSvxS_HKJQxvyZL_SGHL-nQW_5nR70l6GWVz9jUNI3DTyf12XubTO2ZHk3Wr4cNlbz4p4XISbxbF7nvO5bGi_ZWacHR1cHnbLl40OVF0H5unjK52VgENNNkKEiUAqETrXJfBFKqkzDikAkK0RSxoto48S0GBuBCpTO0pQi3cURQjRluL9r7Oicpa5Z2_5T220Dotnhaf7xNDs8zQGPD93uQ2vtjB466__s3TGJSYISs9Tv3ez3eiI62gmKLBYy-gPkFGgM</recordid><startdate>20121101</startdate><enddate>20121101</enddate><creator>LIAO, Yuan-Hsin</creator><creator>LI, Gwo-Long</creator><creator>CHANG, Tian-Sheuan</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20121101</creationdate><title>A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video</title><author>LIAO, Yuan-Hsin ; LI, Gwo-Long ; CHANG, Tian-Sheuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c227t-928e18810a7ac9a7a08589a1be106b22e8c6b20d46cd24c02818a977e3af43213</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Coding, codes</topic><topic>Context-adaptive variable length decoder (CAVLD)</topic><topic>Decoding</topic><topic>Delay</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Encoding</topic><topic>Exact sciences and technology</topic><topic>H.264</topic><topic>Image processing</topic><topic>Information, signal and communications theory</topic><topic>Integrated circuits</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal and communications theory</topic><topic>Signal convertors</topic><topic>Signal processing</topic><topic>Telecommunications and information theory</topic><topic>Throughput</topic><topic>Video coding</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>LIAO, Yuan-Hsin</creatorcontrib><creatorcontrib>LI, Gwo-Long</creatorcontrib><creatorcontrib>CHANG, Tian-Sheuan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on circuits and systems for video technology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIAO, Yuan-Hsin</au><au>LI, Gwo-Long</au><au>CHANG, Tian-Sheuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video</atitle><jtitle>IEEE transactions on circuits and systems for video technology</jtitle><stitle>TCSVT</stitle><date>2012-11-01</date><risdate>2012</risdate><volume>22</volume><issue>11</issue><spage>1604</spage><epage>1610</epage><pages>1604-1610</pages><issn>1051-8215</issn><eissn>1558-2205</eissn><coden>ITCTEM</coden><abstract>To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54k gate counts under 90-nm CMOS technology.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TCSVT.2012.2202081</doi><tpages>7</tpages></addata></record> |
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| ispartof | IEEE transactions on circuits and systems for video technology, 2012-11, Vol.22 (11), p.1604-1610 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit properties Coding, codes Context-adaptive variable length decoder (CAVLD) Decoding Delay Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Encoding Exact sciences and technology H.264 Image processing Information, signal and communications theory Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal and communications theory Signal convertors Signal processing Telecommunications and information theory Throughput Video coding |
| title | A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T14%3A22%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20385%20MHz%2013.54%20K%20Gates%20Delay%20Balanced%20Two-Level%20CAVLC%20Decoder%20for%20Ultra%20HD%20H.264/AVC%20Video&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems%20for%20video%20technology&rft.au=LIAO,%20Yuan-Hsin&rft.date=2012-11-01&rft.volume=22&rft.issue=11&rft.spage=1604&rft.epage=1610&rft.pages=1604-1610&rft.issn=1051-8215&rft.eissn=1558-2205&rft.coden=ITCTEM&rft_id=info:doi/10.1109/TCSVT.2012.2202081&rft_dat=%3Cpascalfrancis_RIE%3E26625297%3C/pascalfrancis_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6209405&rfr_iscdi=true |