Cost estimation of nanoscale partial defect tolerant arrays

High defect rates are common in nanotechnology and fabrication has to deal with increasing variations and percent of mortality rates. Qualitative changes are introduced in circuit design to make nanoscale architectures less prone to defects. Fault tolerant techniques will be crucial to the use of na...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Simic, V., Ciric, V., Milentijevic, I.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Fabrication Fault tolerance Fault tolerant systems Nanoscale devices Topology
Online-Zugang:	Volltext bestellen
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