New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor

New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor

We have developed a new test method for evaluating low-k materials. The method uses two kinds of new test structures. One is a modified gated pn-junction diode and the other is a modified field MOS transistor. Three kinds of low-k materials were evaluated by using the test structures, and electrical...

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Hauptverfasser: Tamaki, Y., Ito, M., Hashino, M., Kawamoto, Y.
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Copper
Logic gates
Voltage measurement
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Ito, M.
Hashino, M.
Kawamoto, Y.
description We have developed a new test method for evaluating low-k materials. The method uses two kinds of new test structures. One is a modified gated pn-junction diode and the other is a modified field MOS transistor. Three kinds of low-k materials were evaluated by using the test structures, and electrical characteristics for these materials were successfully measured. The advantage of the new method was discussed.
doi_str_mv 10.1109/ICMTS.2012.6190632
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6190632</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6190632</ieee_id><sourcerecordid>6190632</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-21b9a54a08f5fc0f6b4138b4162bf39b873dd5575051162bfc47a950a029f1c33</originalsourceid><addsrcrecordid>eNpFUNlOwzAQNJdEKf0BePEPuHjtOI4fUcVRqQdSy3PlxHZxyYFih6p_TyiV2IcdzYxmpVmE7oCOAah6mE7m69WYUWDjFBRNOTtDN5CkkgNlKjtHAwYiI7_k4t-QcIkGQCUQRTm7RqMQdrQfSblQbICqhd1j-63LTkff1Liy8aMxuHG4bPbkExtvS1vE1hfY-bIKOD_gLvh6izXe6mgNfluQXVcXx7TxjbFY16Z3XZ80eL5c4djqOvgQm_YWXTldBjs64RC9Pz-tJ69ktnyZTh5nxIMUkTDIlRaJppkTrqAuzRPgWb9Sljuu8kxyY4SQggo4akUitRJU990dFJwP0f3fXW-t3Xy1vtLtYXN6G_8BHx1cjQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Tamaki, Y. ; Ito, M. ; Hashino, M. ; Kawamoto, Y.</creator><creatorcontrib>Tamaki, Y. ; Ito, M. ; Hashino, M. ; Kawamoto, Y.</creatorcontrib><description>We have developed a new test method for evaluating low-k materials. The method uses two kinds of new test structures. One is a modified gated pn-junction diode and the other is a modified field MOS transistor. Three kinds of low-k materials were evaluated by using the test structures, and electrical characteristics for these materials were successfully measured. The advantage of the new method was discussed.</description><identifier>ISSN: 1071-9032</identifier><identifier>ISBN: 1467310271</identifier><identifier>ISBN: 9781467310277</identifier><identifier>EISSN: 2158-1029</identifier><identifier>EISBN: 1467310298</identifier><identifier>EISBN: 1467310301</identifier><identifier>EISBN: 9781467310307</identifier><identifier>EISBN: 9781467310291</identifier><identifier>DOI: 10.1109/ICMTS.2012.6190632</identifier><language>eng</language><publisher>IEEE</publisher><subject>Copper ; Logic gates ; Voltage measurement</subject><ispartof>2012 IEEE International Conference on Microelectronic Test Structures, 2012, p.137-141</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6190632$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6190632$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tamaki, Y.</creatorcontrib><creatorcontrib>Ito, M.</creatorcontrib><creatorcontrib>Hashino, M.</creatorcontrib><creatorcontrib>Kawamoto, Y.</creatorcontrib><title>New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor</title><title>2012 IEEE International Conference on Microelectronic Test Structures</title><addtitle>ICMTS</addtitle><description>We have developed a new test method for evaluating low-k materials. The method uses two kinds of new test structures. One is a modified gated pn-junction diode and the other is a modified field MOS transistor. Three kinds of low-k materials were evaluated by using the test structures, and electrical characteristics for these materials were successfully measured. The advantage of the new method was discussed.</description><subject>Copper</subject><subject>Logic gates</subject><subject>Voltage measurement</subject><issn>1071-9032</issn><issn>2158-1029</issn><isbn>1467310271</isbn><isbn>9781467310277</isbn><isbn>1467310298</isbn><isbn>1467310301</isbn><isbn>9781467310307</isbn><isbn>9781467310291</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUNlOwzAQNJdEKf0BePEPuHjtOI4fUcVRqQdSy3PlxHZxyYFih6p_TyiV2IcdzYxmpVmE7oCOAah6mE7m69WYUWDjFBRNOTtDN5CkkgNlKjtHAwYiI7_k4t-QcIkGQCUQRTm7RqMQdrQfSblQbICqhd1j-63LTkff1Liy8aMxuHG4bPbkExtvS1vE1hfY-bIKOD_gLvh6izXe6mgNfluQXVcXx7TxjbFY16Z3XZ80eL5c4djqOvgQm_YWXTldBjs64RC9Pz-tJ69ktnyZTh5nxIMUkTDIlRaJppkTrqAuzRPgWb9Sljuu8kxyY4SQggo4akUitRJU990dFJwP0f3fXW-t3Xy1vtLtYXN6G_8BHx1cjQ</recordid><startdate>201203</startdate><enddate>201203</enddate><creator>Tamaki, Y.</creator><creator>Ito, M.</creator><creator>Hashino, M.</creator><creator>Kawamoto, Y.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201203</creationdate><title>New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor</title><author>Tamaki, Y. ; Ito, M. ; Hashino, M. ; Kawamoto, Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-21b9a54a08f5fc0f6b4138b4162bf39b873dd5575051162bfc47a950a029f1c33</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Copper</topic><topic>Logic gates</topic><topic>Voltage measurement</topic><toplevel>online_resources</toplevel><creatorcontrib>Tamaki, Y.</creatorcontrib><creatorcontrib>Ito, M.</creatorcontrib><creatorcontrib>Hashino, M.</creatorcontrib><creatorcontrib>Kawamoto, Y.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Explore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tamaki, Y.</au><au>Ito, M.</au><au>Hashino, M.</au><au>Kawamoto, Y.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor</atitle><btitle>2012 IEEE International Conference on Microelectronic Test Structures</btitle><stitle>ICMTS</stitle><date>2012-03</date><risdate>2012</risdate><spage>137</spage><epage>141</epage><pages>137-141</pages><issn>1071-9032</issn><eissn>2158-1029</eissn><isbn>1467310271</isbn><isbn>9781467310277</isbn><eisbn>1467310298</eisbn><eisbn>1467310301</eisbn><eisbn>9781467310307</eisbn><eisbn>9781467310291</eisbn><abstract>We have developed a new test method for evaluating low-k materials. The method uses two kinds of new test structures. One is a modified gated pn-junction diode and the other is a modified field MOS transistor. Three kinds of low-k materials were evaluated by using the test structures, and electrical characteristics for these materials were successfully measured. The advantage of the new method was discussed.</abstract><pub>IEEE</pub><doi>10.1109/ICMTS.2012.6190632</doi><tpages>5</tpages></addata></record>
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subjects Copper
Logic gates
Voltage measurement
title New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T16%3A40%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=New%20evaluation%20method%20of%20low-k%20dielectric%20films%20by%20using%20a%20gated%20PN-junction%20diode%20and%20a%20field%20MOS%20transistor&rft.btitle=2012%20IEEE%20International%20Conference%20on%20Microelectronic%20Test%20Structures&rft.au=Tamaki,%20Y.&rft.date=2012-03&rft.spage=137&rft.epage=141&rft.pages=137-141&rft.issn=1071-9032&rft.eissn=2158-1029&rft.isbn=1467310271&rft.isbn_list=9781467310277&rft_id=info:doi/10.1109/ICMTS.2012.6190632&rft_dat=%3Cieee_6IE%3E6190632%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1467310298&rft.eisbn_list=1467310301&rft.eisbn_list=9781467310307&rft.eisbn_list=9781467310291&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6190632&rfr_iscdi=true