Implementation of 32-bit Ling and Jackson adders
Ling adders factor complexity out of the first stage of an adder to shorten the critical path. In 2004, Jackson and Talwar proposed a generalization of the Ling adder that reduces the complexity of the critical generate path at the expense of increased complexity in the propagate logic. This paper c...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 175 |
|---|---|
| container_issue | |
| container_start_page | 170 |
| container_title | |
| container_volume | |
| creator | Keeter, M. Harris, D. M. Macrae, A. Glick, R. Ong, M. Schauer, J. |
| description | Ling adders factor complexity out of the first stage of an adder to shorten the critical path. In 2004, Jackson and Talwar proposed a generalization of the Ling adder that reduces the complexity of the critical generate path at the expense of increased complexity in the propagate logic. This paper compares implementations of 32-bit Ling and Jackson adders to the optimized Sklansky architecture produced by Design Compiler in a 45 nm process. The Ling adder is 3% faster and uses 7% less energy, achieving a delay of 8.3 FO4 inverters. The Jackson adder is only 1% faster and uses 45% more energy. However, this is the first published implementation of a Jackson adder with all details shown. |
| doi_str_mv | 10.1109/ACSSC.2011.6189978 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6189978</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6189978</ieee_id><sourcerecordid>6189978</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-97d4f183c9356594150bf776b69f727968f5bab7be38b36592b8ecaca77080333</originalsourceid><addsrcrecordid>eNpVT81OwzAYC38S1egLwKUvkJIvX5MvOU4VjKFKHAbnKWkTFFi7qe2Ft6cSu-CDLcuWJTN2D6IEEPZxXe92dSkFQKnBWEvmguULQ6UJBUpZXbJMKtJcLvbqXwZ0zTIQynCNFm9ZPk1fYgEJNJoyJrb96RD6MMxuTsehOMYCJfdpLpo0fBZu6IpX135PS-S6LozTHbuJ7jCF_Kwr9vH89F6_8OZts63XDU9AauaWuiqCwdai0spWoISPRNprG0mS1SYq7zz5gMbj0pDehNa1jkgYgYgr9vC3m0II-9OYejf-7M__8ResQkd9</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Implementation of 32-bit Ling and Jackson adders</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Keeter, M. ; Harris, D. M. ; Macrae, A. ; Glick, R. ; Ong, M. ; Schauer, J.</creator><creatorcontrib>Keeter, M. ; Harris, D. M. ; Macrae, A. ; Glick, R. ; Ong, M. ; Schauer, J.</creatorcontrib><description>Ling adders factor complexity out of the first stage of an adder to shorten the critical path. In 2004, Jackson and Talwar proposed a generalization of the Ling adder that reduces the complexity of the critical generate path at the expense of increased complexity in the propagate logic. This paper compares implementations of 32-bit Ling and Jackson adders to the optimized Sklansky architecture produced by Design Compiler in a 45 nm process. The Ling adder is 3% faster and uses 7% less energy, achieving a delay of 8.3 FO4 inverters. The Jackson adder is only 1% faster and uses 45% more energy. However, this is the first published implementation of a Jackson adder with all details shown.</description><identifier>ISSN: 1058-6393</identifier><identifier>ISBN: 9781467303217</identifier><identifier>ISBN: 1467303216</identifier><identifier>EISSN: 2576-2303</identifier><identifier>EISBN: 9781467303224</identifier><identifier>EISBN: 1467303232</identifier><identifier>EISBN: 9781467303231</identifier><identifier>EISBN: 1467303224</identifier><identifier>DOI: 10.1109/ACSSC.2011.6189978</identifier><language>eng</language><publisher>IEEE</publisher><subject>Adders ; Complexity theory ; Computer architecture ; Delay ; Inverters ; Logic gates ; Microprocessors</subject><ispartof>2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011, p.170-175</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6189978$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6189978$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Keeter, M.</creatorcontrib><creatorcontrib>Harris, D. M.</creatorcontrib><creatorcontrib>Macrae, A.</creatorcontrib><creatorcontrib>Glick, R.</creatorcontrib><creatorcontrib>Ong, M.</creatorcontrib><creatorcontrib>Schauer, J.</creatorcontrib><title>Implementation of 32-bit Ling and Jackson adders</title><title>2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)</title><addtitle>ACSSC</addtitle><description>Ling adders factor complexity out of the first stage of an adder to shorten the critical path. In 2004, Jackson and Talwar proposed a generalization of the Ling adder that reduces the complexity of the critical generate path at the expense of increased complexity in the propagate logic. This paper compares implementations of 32-bit Ling and Jackson adders to the optimized Sklansky architecture produced by Design Compiler in a 45 nm process. The Ling adder is 3% faster and uses 7% less energy, achieving a delay of 8.3 FO4 inverters. The Jackson adder is only 1% faster and uses 45% more energy. However, this is the first published implementation of a Jackson adder with all details shown.</description><subject>Adders</subject><subject>Complexity theory</subject><subject>Computer architecture</subject><subject>Delay</subject><subject>Inverters</subject><subject>Logic gates</subject><subject>Microprocessors</subject><issn>1058-6393</issn><issn>2576-2303</issn><isbn>9781467303217</isbn><isbn>1467303216</isbn><isbn>9781467303224</isbn><isbn>1467303232</isbn><isbn>9781467303231</isbn><isbn>1467303224</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVT81OwzAYC38S1egLwKUvkJIvX5MvOU4VjKFKHAbnKWkTFFi7qe2Ft6cSu-CDLcuWJTN2D6IEEPZxXe92dSkFQKnBWEvmguULQ6UJBUpZXbJMKtJcLvbqXwZ0zTIQynCNFm9ZPk1fYgEJNJoyJrb96RD6MMxuTsehOMYCJfdpLpo0fBZu6IpX135PS-S6LozTHbuJ7jCF_Kwr9vH89F6_8OZts63XDU9AauaWuiqCwdai0spWoISPRNprG0mS1SYq7zz5gMbj0pDehNa1jkgYgYgr9vC3m0II-9OYejf-7M__8ResQkd9</recordid><startdate>201111</startdate><enddate>201111</enddate><creator>Keeter, M.</creator><creator>Harris, D. M.</creator><creator>Macrae, A.</creator><creator>Glick, R.</creator><creator>Ong, M.</creator><creator>Schauer, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201111</creationdate><title>Implementation of 32-bit Ling and Jackson adders</title><author>Keeter, M. ; Harris, D. M. ; Macrae, A. ; Glick, R. ; Ong, M. ; Schauer, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-97d4f183c9356594150bf776b69f727968f5bab7be38b36592b8ecaca77080333</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Adders</topic><topic>Complexity theory</topic><topic>Computer architecture</topic><topic>Delay</topic><topic>Inverters</topic><topic>Logic gates</topic><topic>Microprocessors</topic><toplevel>online_resources</toplevel><creatorcontrib>Keeter, M.</creatorcontrib><creatorcontrib>Harris, D. M.</creatorcontrib><creatorcontrib>Macrae, A.</creatorcontrib><creatorcontrib>Glick, R.</creatorcontrib><creatorcontrib>Ong, M.</creatorcontrib><creatorcontrib>Schauer, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Keeter, M.</au><au>Harris, D. M.</au><au>Macrae, A.</au><au>Glick, R.</au><au>Ong, M.</au><au>Schauer, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Implementation of 32-bit Ling and Jackson adders</atitle><btitle>2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)</btitle><stitle>ACSSC</stitle><date>2011-11</date><risdate>2011</risdate><spage>170</spage><epage>175</epage><pages>170-175</pages><issn>1058-6393</issn><eissn>2576-2303</eissn><isbn>9781467303217</isbn><isbn>1467303216</isbn><eisbn>9781467303224</eisbn><eisbn>1467303232</eisbn><eisbn>9781467303231</eisbn><eisbn>1467303224</eisbn><abstract>Ling adders factor complexity out of the first stage of an adder to shorten the critical path. In 2004, Jackson and Talwar proposed a generalization of the Ling adder that reduces the complexity of the critical generate path at the expense of increased complexity in the propagate logic. This paper compares implementations of 32-bit Ling and Jackson adders to the optimized Sklansky architecture produced by Design Compiler in a 45 nm process. The Ling adder is 3% faster and uses 7% less energy, achieving a delay of 8.3 FO4 inverters. The Jackson adder is only 1% faster and uses 45% more energy. However, this is the first published implementation of a Jackson adder with all details shown.</abstract><pub>IEEE</pub><doi>10.1109/ACSSC.2011.6189978</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1058-6393 |
| ispartof | 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011, p.170-175 |
| issn | 1058-6393 2576-2303 |
| language | eng |
| recordid | cdi_ieee_primary_6189978 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adders Complexity theory Computer architecture Delay Inverters Logic gates Microprocessors |
| title | Implementation of 32-bit Ling and Jackson adders |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T19%3A53%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Implementation%20of%2032-bit%20Ling%20and%20Jackson%20adders&rft.btitle=2011%20Conference%20Record%20of%20the%20Forty%20Fifth%20Asilomar%20Conference%20on%20Signals,%20Systems%20and%20Computers%20(ASILOMAR)&rft.au=Keeter,%20M.&rft.date=2011-11&rft.spage=170&rft.epage=175&rft.pages=170-175&rft.issn=1058-6393&rft.eissn=2576-2303&rft.isbn=9781467303217&rft.isbn_list=1467303216&rft_id=info:doi/10.1109/ACSSC.2011.6189978&rft_dat=%3Cieee_6IE%3E6189978%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781467303224&rft.eisbn_list=1467303232&rft.eisbn_list=9781467303231&rft.eisbn_list=1467303224&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6189978&rfr_iscdi=true |