Board level solder joint reliability modeling of Embedded Wafer Level BGA (eWLB) packages under temperature cycling test conditions

Embedded Wafer-Level Ball Grid Array (eWLB) technology was developed to provide a wafer-level packaging solution for semiconductor devices requiring a higher integration level and a greater number of external contacts. Essentially, eWLB is a fan-out wafer-level packaging in which silicon die is embedded in the mold compound and the redistributed layer can be carried out over both silicon die and mold compound areas. Although many solder joint thermal fatigue models have been published for BGA and WLCSP packages, they may not be applicable for the eWLB packages. In this paper, the board level solder fatigue life modeling for lead-free solder Sn96.5Ag3.0Cu0.5 (SAC305) used in embedded Wafer Level Ball Grid Array (eWLB) packages under temperature cycling test conditions will be presented. Thermal fatigue life models, associated with Anand viscoplastic constitutive model used for the solder material, are first established by curve-fitting the equivalent creep strain and creep strain energy density data, respectively, with temperature cycling test data. A series of numerical parameter studies is then carried out on various design parameters such as material properties, configurations of packages and test boards, and temperature cycling test conditions. The effects of coefficient of thermal expansion (CTE) mismatch and bending stiffness of the eWLB package assemblies on the solder joint lifetime and the shift of critical solder joint locations will be discussed.