Design and Analysis of a W-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique
In this paper, we present design and analysis of a W -band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, a...
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| Veröffentlicht in: | IEEE transactions on microwave theory and techniques 2012-06, Vol.60 (6), p.1617-1625 |
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| creator | YEH, Yen-Liang CHANG, Hong-Yeh |
| description | In this paper, we present design and analysis of a W -band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W -Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V. |
| doi_str_mv | 10.1109/TMTT.2012.2189244 |
| format | Article |
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Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W -Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V.</description><identifier>ISSN: 0018-9480</identifier><identifier>EISSN: 1557-9670</identifier><identifier>DOI: 10.1109/TMTT.2012.2189244</identifier><identifier>CODEN: IETMAB</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Capacitance ; Circuit properties ; Circuits of signal characteristics conditioning (including delay circuits) ; CMOS ; Design engineering ; Design. Technologies. Operation analysis. Testing ; Direct current ; divide-by-three ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Frequency conversion ; Frequency dividers ; Harmonic analysis ; Harmonics ; Inductors ; injection-locked frequency divider (ILFD) ; Injectors ; Integrated circuits ; Locking ; Oscillators ; Oscillators, resonators, synthetizers ; phase-locked loop (PLL) ; Power consumption ; Power demand ; Q factor ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal convertors ; Tuning</subject><ispartof>IEEE transactions on microwave theory and techniques, 2012-06, Vol.60 (6), p.1617-1625</ispartof><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c328t-3cea6c534f29ad3ea7a00d774475e2d0bddfe8e483e37d8c31c20fef391d1d393</citedby><cites>FETCH-LOGICAL-c328t-3cea6c534f29ad3ea7a00d774475e2d0bddfe8e483e37d8c31c20fef391d1d393</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6177292$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6177292$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=25982681$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>YEH, Yen-Liang</creatorcontrib><creatorcontrib>CHANG, Hong-Yeh</creatorcontrib><title>Design and Analysis of a W-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique</title><title>IEEE transactions on microwave theory and techniques</title><addtitle>TMTT</addtitle><description>In this paper, we present design and analysis of a W -band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W -Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V.</description><subject>Applied sciences</subject><subject>Capacitance</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>CMOS</subject><subject>Design engineering</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Direct current</subject><subject>divide-by-three</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Frequency conversion</subject><subject>Frequency dividers</subject><subject>Harmonic analysis</subject><subject>Harmonics</subject><subject>Inductors</subject><subject>injection-locked frequency divider (ILFD)</subject><subject>Injectors</subject><subject>Integrated circuits</subject><subject>Locking</subject><subject>Oscillators</subject><subject>Oscillators, resonators, synthetizers</subject><subject>phase-locked loop (PLL)</subject><subject>Power consumption</subject><subject>Power demand</subject><subject>Q factor</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal convertors</subject><subject>Tuning</subject><issn>0018-9480</issn><issn>1557-9670</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE9LwzAYh4MoOKcfQLzkInjJzJ-2SY6imw4mHuzwWLLkrYt2qSZT6MXPbsvGTiHJ8_u9vA9Cl4xOGKP6tnwuywmnjE84U5pn2REasTyXRBeSHqMRpUwRnSl6is5S-uivWU7VCP09QPLvAZvg8F0wTZd8wm2NDX4jq-Hxwf96B2TVkXIdAfA8fIDd-jaQRWs_weFZhO8fCLbboxEvkw_v-BVs2-efTNy0wVs8DWsTLGwgbHEJdh18HztHJ7VpElzszzFazqbl_RNZvDzO7-8WxAqutkRYMIXNRVZzbZwAIw2lTsoskzlwR1fO1aAgUwKEdMoKZjmtoRaaOeaEFmN0s-v9im0_Nm2rjU8WmsYEaH9S1avSRc5zNqBsh9rYphShrr6i35jYVYxWg-tqcF0Nrqu96z5zva83yZqmjv2mPh2CPNeKF4r13NWO8wBw-C6YlFxz8Q-afIka</recordid><startdate>20120601</startdate><enddate>20120601</enddate><creator>YEH, Yen-Liang</creator><creator>CHANG, Hong-Yeh</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>20120601</creationdate><title>Design and Analysis of a W-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique</title><author>YEH, Yen-Liang ; CHANG, Hong-Yeh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c328t-3cea6c534f29ad3ea7a00d774475e2d0bddfe8e483e37d8c31c20fef391d1d393</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Applied sciences</topic><topic>Capacitance</topic><topic>Circuit properties</topic><topic>Circuits of signal characteristics conditioning (including delay circuits)</topic><topic>CMOS</topic><topic>Design engineering</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Direct current</topic><topic>divide-by-three</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Frequency conversion</topic><topic>Frequency dividers</topic><topic>Harmonic analysis</topic><topic>Harmonics</topic><topic>Inductors</topic><topic>injection-locked frequency divider (ILFD)</topic><topic>Injectors</topic><topic>Integrated circuits</topic><topic>Locking</topic><topic>Oscillators</topic><topic>Oscillators, resonators, synthetizers</topic><topic>phase-locked loop (PLL)</topic><topic>Power consumption</topic><topic>Power demand</topic><topic>Q factor</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal convertors</topic><topic>Tuning</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>YEH, Yen-Liang</creatorcontrib><creatorcontrib>CHANG, Hong-Yeh</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on microwave theory and techniques</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YEH, Yen-Liang</au><au>CHANG, Hong-Yeh</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design and Analysis of a W-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique</atitle><jtitle>IEEE transactions on microwave theory and techniques</jtitle><stitle>TMTT</stitle><date>2012-06-01</date><risdate>2012</risdate><volume>60</volume><issue>6</issue><spage>1617</spage><epage>1625</epage><pages>1617-1625</pages><issn>0018-9480</issn><eissn>1557-9670</eissn><coden>IETMAB</coden><abstract>In this paper, we present design and analysis of a W -band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W -Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TMTT.2012.2189244</doi><tpages>9</tpages></addata></record> |
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| subjects | Applied sciences Capacitance Circuit properties Circuits of signal characteristics conditioning (including delay circuits) CMOS Design engineering Design. Technologies. Operation analysis. Testing Direct current divide-by-three Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Frequency conversion Frequency dividers Harmonic analysis Harmonics Inductors injection-locked frequency divider (ILFD) Injectors Integrated circuits Locking Oscillators Oscillators, resonators, synthetizers phase-locked loop (PLL) Power consumption Power demand Q factor Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Tuning |
| title | Design and Analysis of a W-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique |
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