A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture

We present a sensing scheme with local bitline sense amplifier (L-BLSA) for sub-1V DRAM core operation, which activates a low-Vt latch locally in time, the same as [1] but shares a common ground with a high-Vt latch. Hybrid LIO sense amplifier (H-LSA) is developed for robust LIO read operation at lo...

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Hauptverfasser:	Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong
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Sprache:	eng
Schlagworte:	Arrays Capacitance Couplings Random access memory Sensors Solids
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creator	Kyu-Nam Lim Woong-Ju Jang Hyung-Sik Won Kang-Yeol Lee Hyungsoo Kim Dong-Whee Kim Mi-Hyun Cho Seung-Lo Kim Jong-Ho Kang Keun-Woo Park Byung-Tae Jeong
description	We present a sensing scheme with local bitline sense amplifier (L-BLSA) for sub-1V DRAM core operation, which activates a low-Vt latch locally in time, the same as [1] but shares a common ground with a high-Vt latch. Hybrid LIO sense amplifier (H-LSA) is developed for robust LIO read operation at low voltage and high clock frequency. In order to reduce the die area, we develop a dummy-less 6F 2 array architecture with no edge dummy array. These schemes are employed in a 1.2V 23nm 6F 2 4Gb DDR3 SDRAM.
doi_str_mv	10.1109/ISSCC.2012.6176870
format	Conference Proceeding
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Arrays Capacitance Couplings Random access memory Sensors Solids
title	A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture
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