A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture
DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional oper...
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| creator | Kibong Koo Sunghwa Ok Yonggu Kang Seungbong Kim Choungki Song Hyeyoung Lee Hyungsoo Kim Yongmi Kim Jeonghun Lee Seunghan Oak Lee, Yosep Jungyu Lee Joongho Lee Hyungyu Lee Jaemin Jang Jongho Jung Byeongchan Choi Yongju Kim Youngdo Hur Yunsaing Kim Byongtae Chung Yongtak Kim |
| description | DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage. |
| doi_str_mv | 10.1109/ISSCC.2012.6176869 |
| format | Conference Proceeding |
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Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage.</description><subject>Current measurement</subject><subject>Delta modulation</subject><subject>Parity check codes</subject><subject>SDRAM</subject><subject>Semiconductor device measurement</subject><subject>Timing</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>1467303763</isbn><isbn>9781467303767</isbn><isbn>9781467303774</isbn><isbn>1467303771</isbn><isbn>9781467303743</isbn><isbn>1467303747</isbn><isbn>9781467303750</isbn><isbn>1467303755</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9zztSwzAUQNHHbwYHsgFo3gYsP30iyWXGDgkFTQy0GTkosSAxHtkZhpWwIDZGE9pUtzjVBbjjxDinPHusqqJggrhgmhttdX4G49xYrrSRJI1R55AIaXRqNekLGP2DlpeQEM9lqieSrmHU9-9ENMm1TeBlipyJV5S23aNgal5nfdaFFsW8xrJcKqzK5fQJv8LQYO3aD9zGz0OHrn3D3x-Fjdtt0s5tPbq4bsLg18Mh-lu42rhd78fH3sD9w-y5WKTBe7_qYti7-L06bsjT-gfB10Kd</recordid><startdate>201202</startdate><enddate>201202</enddate><creator>Kibong Koo</creator><creator>Sunghwa Ok</creator><creator>Yonggu Kang</creator><creator>Seungbong Kim</creator><creator>Choungki Song</creator><creator>Hyeyoung Lee</creator><creator>Hyungsoo Kim</creator><creator>Yongmi Kim</creator><creator>Jeonghun Lee</creator><creator>Seunghan Oak</creator><creator>Lee, Yosep</creator><creator>Jungyu Lee</creator><creator>Joongho Lee</creator><creator>Hyungyu Lee</creator><creator>Jaemin Jang</creator><creator>Jongho Jung</creator><creator>Byeongchan Choi</creator><creator>Yongju Kim</creator><creator>Youngdo Hur</creator><creator>Yunsaing Kim</creator><creator>Byongtae Chung</creator><creator>Yongtak Kim</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201202</creationdate><title>A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture</title><author>Kibong Koo ; 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In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2012.6176869</doi></addata></record> |
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| identifier | ISSN: 0193-6530 |
| ispartof | 2012 IEEE International Solid-State Circuits Conference, 2012, p.40-41 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_6176869 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Current measurement Delta modulation Parity check codes SDRAM Semiconductor device measurement Timing |
| title | A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture |
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