An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture

Network on chip (NoC) architecture is viewed as a potential solution for the interconnect demands of the emerging multi-core systems since it renders the system high performance, flexibility and low-cost. Mapping tasks onto different cores of the network is a critical phase in NoC design because it...

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Bibliographische Detailangaben

Hauptverfasser:	Liulin Zhong, Jiayi Sheng, Ming'e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Artificial neural networks mapping multi-core system NoC Optimization Pipelines Simulated Annealing
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