The DAQ readout chain of the DSSC detector at the European XFEL

The DSSC collaboration is developing an instrument to detect synchrotron X-rays (E >; 0.5 keV) at the European XFEL. The DEPFET based sensors with integrated signal compression will be read out by 16 dedicated readout ASICs per sensor main board. Data are acquired during the XFEL burst (≈ 600 μs) at a rate of up to 4.5 MHz, and subsequently read out by the DAQ readout chain during the approximately 99.4 ms long burst gaps. The DAQ readout chain comprises two FPGA-based detector specific modules (I/O Board and Patch Panel Transceiver), which will be described in detail. A concentrator stage (Trainbuilder), which is common to all 2D detectors and part of the general XFEL DAQ, receives the data, and forwards them to the back-end storage facility. Each sensor main board has an I/O Board. Its purpose is to concentrate the data of the 16 low-speed channels of the ASICs into four high-speed serial links. The I/O Board also controls the shutdown of the analog sections during the readout phase to minimize the power consumption of the DSSC detector. The accumulated data will be sent to the Patch Panel Transceivers residing on the head of the detector. A Patch Panel Transceiver receives the XFEL front-end electronics (FEE) clock (≈ 99 MHz) and commands from the master Clock & Control unit. In addition, it provides the ASICs with control telegrams generated by the FPGA. An on-board PLL generates the ADC sampling clock of approximately 700 MHz, which is derived from, and in phase with the XFEL FEE clock.