Porting irregular reductions on heterogeneous CPU-GPU configurations

Heterogeneous architectures are playing a significant role in High Performance Computing (HPC) today, with the popularity of accelerators like the GPUs, and the new trend towards the integration of CPUs and GPUs. Developing applications that can effectively use these architectures is a major challen...

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Bibliographische Detailangaben

Hauptverfasser:	Xin Huo, Ravi, V. T., Agrawal, G.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arrays Central Processing Unit Graphics processing unit Instruction sets Pipeline processing Runtime
Online-Zugang:	Volltext bestellen
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