A technique to eliminate glitch power consumption at physical design stage in CMOS circuits

A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow. A glitch is an undesired transition that oc...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kumar, Vasantha B. V. P., Sharma, N. S. Murthy, Kishore, K. Lal, Vivekanand, M., Raju, K. Murthy, Swetha, S. Divya
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS delay devices CMOS integrated circuits Delay digital logic circuits dynamic power glitches Logic circuits Logic gates low power design Power demand Resistance simulation Transistors
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