Techniques to improve memory interface test quality for complex SoCs

Aggressive speed and voltage binning schemes are widely used in the industry to improve the yield of SoCs. For accurate bin classification, it is essential that the tests used for binning target the worst critical/speed-limiting paths in the design. We have observed in many SoCs that memory interfac...

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Bibliographische Detailangaben

Hauptverfasser:	Devanathan, V. R., Vooka, S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arrays Automatic test pattern generation Built-in self-test Clocks Random access memory System-on-a-chip Timing
Online-Zugang:	Volltext bestellen
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