Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process
The Application Specific Integrated Circuit (ASIC) design approach depends highly on the quality of the cell library to meet design specifications. Due to the use of both digital and analog signal processing, mixed-signal integrated circuits library are usually designed for specific purposes and the...
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| creator | Chun Zhao Zhang, W. Zhao, C. Z. Man, K. L. Jeong, T. T. Seon, J. K. Lee, Y. |
| description | The Application Specific Integrated Circuit (ASIC) design approach depends highly on the quality of the cell library to meet design specifications. Due to the use of both digital and analog signal processing, mixed-signal integrated circuits library are usually designed for specific purposes and the related design requires a high level of expertise and careful use of computer aided design tools. The paper establishes a series of standard cell: scan D flip-flops based on 0.5 micron complementary metal oxide semiconductor mixed-signal process. The research work presented in this paper includes reverse engineering, standard cell schematic and symbol building, standard cell layout drawing and post layout simulation. |
| doi_str_mv | 10.1109/ISOCC.2011.6138771 |
| format | Conference Proceeding |
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Z. ; Man, K. L. ; Jeong, T. T. ; Seon, J. K. ; Lee, Y.</creator><creatorcontrib>Chun Zhao ; Zhang, W. ; Zhao, C. Z. ; Man, K. L. ; Jeong, T. T. ; Seon, J. K. ; Lee, Y.</creatorcontrib><description>The Application Specific Integrated Circuit (ASIC) design approach depends highly on the quality of the cell library to meet design specifications. Due to the use of both digital and analog signal processing, mixed-signal integrated circuits library are usually designed for specific purposes and the related design requires a high level of expertise and careful use of computer aided design tools. The paper establishes a series of standard cell: scan D flip-flops based on 0.5 micron complementary metal oxide semiconductor mixed-signal process. The research work presented in this paper includes reverse engineering, standard cell schematic and symbol building, standard cell layout drawing and post layout simulation.</description><identifier>ISBN: 1457707098</identifier><identifier>ISBN: 9781457707094</identifier><identifier>EISBN: 9781457707117</identifier><identifier>EISBN: 9781457707100</identifier><identifier>EISBN: 1457707101</identifier><identifier>EISBN: 145770711X</identifier><identifier>DOI: 10.1109/ISOCC.2011.6138771</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>IC Design ; Layout ; Scan D Flip-Flops ; Standard Cell Library ; Tanner ED A Tools</subject><ispartof>2011 International SoC Design Conference, 2011, p.306-309</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6138771$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6138771$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chun Zhao</creatorcontrib><creatorcontrib>Zhang, W.</creatorcontrib><creatorcontrib>Zhao, C. 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The research work presented in this paper includes reverse engineering, standard cell schematic and symbol building, standard cell layout drawing and post layout simulation.</description><subject>IC Design</subject><subject>Layout</subject><subject>Scan D Flip-Flops</subject><subject>Standard Cell Library</subject><subject>Tanner ED A Tools</subject><isbn>1457707098</isbn><isbn>9781457707094</isbn><isbn>9781457707117</isbn><isbn>9781457707100</isbn><isbn>1457707101</isbn><isbn>145770711X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkFtLxDAQhSMiqGv_gL7kD7Rmtm0uj1JvCyt9qD4vSTrVSHohqaL_3oA7L-cczjDwDSHXwAoApm53Xds0xZYBFBxKKQSckEwJCVUtBBMA4pRcHgNT8pxkMX6yNJwryeGCfHernnodemrRe-qdCTr8UoyrNt7FjxGnlaYNGt345fXq5okOc6DR6one08G7JR_8vERqdMSeppoVNR2dDck2L22X_A_2eXTvk_Z0CbPFGK_I2aB9xOyoG_L2-PDaPOf79mnX3O1zBzVfczBYCkAmDCjYSl6pgVvNLTcIUnIuUJQ2waFRrC_ZwHstqkoyxRO5gbrckJv_uw4RD0twY6I7HF9V_gH7HVzD</recordid><startdate>201111</startdate><enddate>201111</enddate><creator>Chun Zhao</creator><creator>Zhang, W.</creator><creator>Zhao, C. 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| language | eng ; jpn |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | IC Design Layout Scan D Flip-Flops Standard Cell Library Tanner ED A Tools |
| title | Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process |
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