A vector coprocessor architecture for embedded systems

We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using sev...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Yi Ge, Takebe, Y., Toichi, M., Mouri, M., Ito, M., Hirose, Y., Takahashi, H.
Format: Tagungsbericht
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 198
container_issue
container_start_page 195
container_title
container_volume
creator Yi Ge
Takebe, Y.
Toichi, M.
Mouri, M.
Ito, M.
Hirose, Y.
Takahashi, H.
description We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using several programs. The evaluation showed that our DSP performs 40 times faster than scalar CPU. The peak performance is 12GOPS@250MHz.
doi_str_mv 10.1109/ISOCC.2011.6138743
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6138743</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6138743</ieee_id><sourcerecordid>6138743</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-d28f0fad59197056bc4e1f775cea6a7f96659a323cd2327e8d2f7e571afcc5153</originalsourceid><addsrcrecordid>eNotj81qwzAQhBVKIG3qF2gufgG7WsnSSsdg-hMI5NDcgyKtiEuMg-QW8vY11HOZme8wMIy9AK8BuH3dfR3athYcoNYgDTZywQqLBhqFyBEAH9jTXLg1K1bk_M0naW2Nhkemt-Uv-XFIpR9uafCU85Rd8pdunPhPojJOgPozhUChzPc8Up-f2TK6a6Zi9jU7vr8d289qf_jYtdt91Vk-VkGYyKMLyoJFrvTZNwQRUXly2mG0WivrpJA-CCmQTBARSSG46L0CJdds8z_bEdHplrrepftpfir_AM2bR3o</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A vector coprocessor architecture for embedded systems</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Yi Ge ; Takebe, Y. ; Toichi, M. ; Mouri, M. ; Ito, M. ; Hirose, Y. ; Takahashi, H.</creator><creatorcontrib>Yi Ge ; Takebe, Y. ; Toichi, M. ; Mouri, M. ; Ito, M. ; Hirose, Y. ; Takahashi, H.</creatorcontrib><description>We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using several programs. The evaluation showed that our DSP performs 40 times faster than scalar CPU. The peak performance is 12GOPS@250MHz.</description><identifier>ISBN: 1457707098</identifier><identifier>ISBN: 9781457707094</identifier><identifier>EISBN: 9781457707117</identifier><identifier>EISBN: 9781457707100</identifier><identifier>EISBN: 1457707101</identifier><identifier>EISBN: 145770711X</identifier><identifier>DOI: 10.1109/ISOCC.2011.6138743</identifier><language>eng</language><publisher>IEEE</publisher><ispartof>2011 International SoC Design Conference, 2011, p.195-198</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6138743$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6138743$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yi Ge</creatorcontrib><creatorcontrib>Takebe, Y.</creatorcontrib><creatorcontrib>Toichi, M.</creatorcontrib><creatorcontrib>Mouri, M.</creatorcontrib><creatorcontrib>Ito, M.</creatorcontrib><creatorcontrib>Hirose, Y.</creatorcontrib><creatorcontrib>Takahashi, H.</creatorcontrib><title>A vector coprocessor architecture for embedded systems</title><title>2011 International SoC Design Conference</title><addtitle>ISOCC</addtitle><description>We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using several programs. The evaluation showed that our DSP performs 40 times faster than scalar CPU. The peak performance is 12GOPS@250MHz.</description><isbn>1457707098</isbn><isbn>9781457707094</isbn><isbn>9781457707117</isbn><isbn>9781457707100</isbn><isbn>1457707101</isbn><isbn>145770711X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81qwzAQhBVKIG3qF2gufgG7WsnSSsdg-hMI5NDcgyKtiEuMg-QW8vY11HOZme8wMIy9AK8BuH3dfR3athYcoNYgDTZywQqLBhqFyBEAH9jTXLg1K1bk_M0naW2Nhkemt-Uv-XFIpR9uafCU85Rd8pdunPhPojJOgPozhUChzPc8Up-f2TK6a6Zi9jU7vr8d289qf_jYtdt91Vk-VkGYyKMLyoJFrvTZNwQRUXly2mG0WivrpJA-CCmQTBARSSG46L0CJdds8z_bEdHplrrepftpfir_AM2bR3o</recordid><startdate>201111</startdate><enddate>201111</enddate><creator>Yi Ge</creator><creator>Takebe, Y.</creator><creator>Toichi, M.</creator><creator>Mouri, M.</creator><creator>Ito, M.</creator><creator>Hirose, Y.</creator><creator>Takahashi, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201111</creationdate><title>A vector coprocessor architecture for embedded systems</title><author>Yi Ge ; Takebe, Y. ; Toichi, M. ; Mouri, M. ; Ito, M. ; Hirose, Y. ; Takahashi, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-d28f0fad59197056bc4e1f775cea6a7f96659a323cd2327e8d2f7e571afcc5153</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Yi Ge</creatorcontrib><creatorcontrib>Takebe, Y.</creatorcontrib><creatorcontrib>Toichi, M.</creatorcontrib><creatorcontrib>Mouri, M.</creatorcontrib><creatorcontrib>Ito, M.</creatorcontrib><creatorcontrib>Hirose, Y.</creatorcontrib><creatorcontrib>Takahashi, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yi Ge</au><au>Takebe, Y.</au><au>Toichi, M.</au><au>Mouri, M.</au><au>Ito, M.</au><au>Hirose, Y.</au><au>Takahashi, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A vector coprocessor architecture for embedded systems</atitle><btitle>2011 International SoC Design Conference</btitle><stitle>ISOCC</stitle><date>2011-11</date><risdate>2011</risdate><spage>195</spage><epage>198</epage><pages>195-198</pages><isbn>1457707098</isbn><isbn>9781457707094</isbn><eisbn>9781457707117</eisbn><eisbn>9781457707100</eisbn><eisbn>1457707101</eisbn><eisbn>145770711X</eisbn><abstract>We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using several programs. The evaluation showed that our DSP performs 40 times faster than scalar CPU. The peak performance is 12GOPS@250MHz.</abstract><pub>IEEE</pub><doi>10.1109/ISOCC.2011.6138743</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1457707098
ispartof 2011 International SoC Design Conference, 2011, p.195-198
issn
language eng
recordid cdi_ieee_primary_6138743
source IEEE Electronic Library (IEL) Conference Proceedings
title A vector coprocessor architecture for embedded systems
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T20%3A09%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20vector%20coprocessor%20architecture%20for%20embedded%20systems&rft.btitle=2011%20International%20SoC%20Design%20Conference&rft.au=Yi%20Ge&rft.date=2011-11&rft.spage=195&rft.epage=198&rft.pages=195-198&rft.isbn=1457707098&rft.isbn_list=9781457707094&rft_id=info:doi/10.1109/ISOCC.2011.6138743&rft_dat=%3Cieee_6IE%3E6138743%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781457707117&rft.eisbn_list=9781457707100&rft.eisbn_list=1457707101&rft.eisbn_list=145770711X&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6138743&rfr_iscdi=true