Nearly defect-free Ge gate-all-around FETs on Si substrates

The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W fin ) of 52nm and L g of 183nm has I on /I off =10 5 , SS= 130mV/dec, and I on =235 μA/μm at -1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D it =2×10 12 cm -2 eV -1 is used. A novel process...

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Bibliographische Detailangaben

Hauptverfasser:	Shu-Han Hsu, Chun-Lin Chu, Wen-Hsien Tu, Yen-Chun Fu, Po-Jung Sung, Hung-Chih Chang, Yen-Ting Chen, Li-Yaw Cho, Hsu, W., Guang-Li Luo, Liu, C. W., Chenming Hu, Fu-Liang Yang
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Epitaxial growth Etching Fabrication FETs Logic gates Performance evaluation Silicon
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