Nearly defect-free Ge gate-all-around FETs on Si substrates
The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W fin ) of 52nm and L g of 183nm has I on /I off =10 5 , SS= 130mV/dec, and I on =235 μA/μm at -1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D it =2×10 12 cm -2 eV -1 is used. A novel process...
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| creator | Shu-Han Hsu Chun-Lin Chu Wen-Hsien Tu Yen-Chun Fu Po-Jung Sung Hung-Chih Chang Yen-Ting Chen Li-Yaw Cho Hsu, W. Guang-Li Luo Liu, C. W. Chenming Hu Fu-Liang Yang |
| description | The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W fin ) of 52nm and L g of 183nm has I on /I off =10 5 , SS= 130mV/dec, and I on =235 μA/μm at -1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D it =2×10 12 cm -2 eV -1 is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W eff ) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing. |
| doi_str_mv | 10.1109/IEDM.2011.6131676 |
| format | Conference Proceeding |
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W.</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><creatorcontrib>Fu-Liang Yang</creatorcontrib><title>Nearly defect-free Ge gate-all-around FETs on Si substrates</title><title>2011 International Electron Devices Meeting</title><addtitle>IEDM</addtitle><description>The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W fin ) of 52nm and L g of 183nm has I on /I off =10 5 , SS= 130mV/dec, and I on =235 μA/μm at -1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D it =2×10 12 cm -2 eV -1 is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W eff ) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.</description><subject>Epitaxial growth</subject><subject>Etching</subject><subject>Fabrication</subject><subject>FETs</subject><subject>Logic gates</subject><subject>Performance evaluation</subject><subject>Silicon</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>1457705060</isbn><isbn>9781457705069</isbn><isbn>9781457705052</isbn><isbn>1457705044</isbn><isbn>9781457705045</isbn><isbn>1457705052</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kM1Kw0AUhcc_MK19AHEzLzDx3vkfXElba6HqQgV3ZZrcSCS2MpMu-vYGrKuz-A4fnMPYNUKJCOF2OZ89lRIQS4sKrbMnbBKcR22cAwNGnrJCorEC0H2csdE_sHDOCkCrBAb0l2yU8xeAdCaYgt09U0zdgdfUUNWLJhHxBfHP2JOIXSdi2u23NX-Yv2W-2_LXluf9Jvdp4PmKXTSxyzQ55pi9D73po1i9LJbT-5VopcbBKWNdIWqieuMjWEOGKtLRqiq6ypELOhiMDpCCddJb0MNcAO-lCsFKNWY3f96WiNY_qf2O6bA-nqB-Aem6SdM</recordid><startdate>201112</startdate><enddate>201112</enddate><creator>Shu-Han Hsu</creator><creator>Chun-Lin Chu</creator><creator>Wen-Hsien Tu</creator><creator>Yen-Chun Fu</creator><creator>Po-Jung Sung</creator><creator>Hung-Chih Chang</creator><creator>Yen-Ting Chen</creator><creator>Li-Yaw Cho</creator><creator>Hsu, W.</creator><creator>Guang-Li Luo</creator><creator>Liu, C. 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W. ; Chenming Hu ; Fu-Liang Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-f2adc114eedb8a065e5ece4a63ca7c7e794951a701e9672860410900882399623</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Epitaxial growth</topic><topic>Etching</topic><topic>Fabrication</topic><topic>FETs</topic><topic>Logic gates</topic><topic>Performance evaluation</topic><topic>Silicon</topic><toplevel>online_resources</toplevel><creatorcontrib>Shu-Han Hsu</creatorcontrib><creatorcontrib>Chun-Lin Chu</creatorcontrib><creatorcontrib>Wen-Hsien Tu</creatorcontrib><creatorcontrib>Yen-Chun Fu</creatorcontrib><creatorcontrib>Po-Jung Sung</creatorcontrib><creatorcontrib>Hung-Chih Chang</creatorcontrib><creatorcontrib>Yen-Ting Chen</creatorcontrib><creatorcontrib>Li-Yaw Cho</creatorcontrib><creatorcontrib>Hsu, W.</creatorcontrib><creatorcontrib>Guang-Li Luo</creatorcontrib><creatorcontrib>Liu, C. W.</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><creatorcontrib>Fu-Liang Yang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shu-Han Hsu</au><au>Chun-Lin Chu</au><au>Wen-Hsien Tu</au><au>Yen-Chun Fu</au><au>Po-Jung Sung</au><au>Hung-Chih Chang</au><au>Yen-Ting Chen</au><au>Li-Yaw Cho</au><au>Hsu, W.</au><au>Guang-Li Luo</au><au>Liu, C. W.</au><au>Chenming Hu</au><au>Fu-Liang Yang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Nearly defect-free Ge gate-all-around FETs on Si substrates</atitle><btitle>2011 International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2011-12</date><risdate>2011</risdate><spage>35.2.1</spage><epage>35.2.4</epage><pages>35.2.1-35.2.4</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>1457705060</isbn><isbn>9781457705069</isbn><eisbn>9781457705052</eisbn><eisbn>1457705044</eisbn><eisbn>9781457705045</eisbn><eisbn>1457705052</eisbn><abstract>The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W fin ) of 52nm and L g of 183nm has I on /I off =10 5 , SS= 130mV/dec, and I on =235 μA/μm at -1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D it =2×10 12 cm -2 eV -1 is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W eff ) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2011.6131676</doi></addata></record> |
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| subjects | Epitaxial growth Etching Fabrication FETs Logic gates Performance evaluation Silicon |
| title | Nearly defect-free Ge gate-all-around FETs on Si substrates |
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