A 10b Ternary SAR ADC with decision time quantization based redundancy
The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent m...
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| creator | Guerber, J. Gande, M. Venkatram, H. Waters, A. Un-Ku Moon |
| description | The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent metastability, residue shaping effects, and stage skipping. A prototype is fabricated in 0.13μm CMOS employing on-chip statistical time reference calibration and supply variability from 0.8 to 1.2V. The chip consumes 84μW at 8 MHz for a FOM of 16fJ/C-S. |
| doi_str_mv | 10.1109/ASSCC.2011.6123605 |
| format | Conference Proceeding |
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The chip consumes 84μW at 8 MHz for a FOM of 16fJ/C-S.</description><subject>Calibration</subject><subject>Capacitors</subject><subject>Clocks</subject><subject>Delay</subject><subject>Quantization</subject><subject>Redundancy</subject><subject>Switches</subject><isbn>9781457717840</isbn><isbn>1457717840</isbn><isbn>9781457717857</isbn><isbn>9781457717833</isbn><isbn>1457717859</isbn><isbn>1457717832</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVT8tKw0AUHZGCUvMDupkfSJw7j9yZZYjWCgWhyb7MJFccsVEzKVK_3ojdeDaHcxbnwdg1iAJAuNuqaeq6kAKgKEGqUpgzljm0oA0ioDV4_k9rccGylF7FjLJ0xupLtqo4iMBbGgc_HnlTbXl1V_OvOL3wnrqY4vvAp7gn_nnwwxS__fTrBJ-o5yP1h6H3Q3e8Yotn_5YoO_GStav7tl7nm6eHx7ra5NGJKZdzJVn0BpwUPnTWBUXSBjTkVE8BhApInVahlFor1BiCQ-Wts0Ybg2rJbv5iIxHtPsa4n0fvTufVD1LbSx0</recordid><startdate>201111</startdate><enddate>201111</enddate><creator>Guerber, J.</creator><creator>Gande, M.</creator><creator>Venkatram, H.</creator><creator>Waters, A.</creator><creator>Un-Ku Moon</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201111</creationdate><title>A 10b Ternary SAR ADC with decision time quantization based redundancy</title><author>Guerber, J. ; Gande, M. ; Venkatram, H. ; Waters, A. ; Un-Ku Moon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-2584e87a51920abc89b3e28b75e93deb103b7ec43b62443747bb973a898545573</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Calibration</topic><topic>Capacitors</topic><topic>Clocks</topic><topic>Delay</topic><topic>Quantization</topic><topic>Redundancy</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>Guerber, J.</creatorcontrib><creatorcontrib>Gande, M.</creatorcontrib><creatorcontrib>Venkatram, H.</creatorcontrib><creatorcontrib>Waters, A.</creatorcontrib><creatorcontrib>Un-Ku Moon</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Guerber, J.</au><au>Gande, M.</au><au>Venkatram, H.</au><au>Waters, A.</au><au>Un-Ku Moon</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 10b Ternary SAR ADC with decision time quantization based redundancy</atitle><btitle>IEEE Asian Solid-State Circuits Conference 2011</btitle><stitle>ASSCC</stitle><date>2011-11</date><risdate>2011</risdate><spage>65</spage><epage>68</epage><pages>65-68</pages><isbn>9781457717840</isbn><isbn>1457717840</isbn><eisbn>9781457717857</eisbn><eisbn>9781457717833</eisbn><eisbn>1457717859</eisbn><eisbn>1457717832</eisbn><abstract>The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. 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| subjects | Calibration Capacitors Clocks Delay Quantization Redundancy Switches |
| title | A 10b Ternary SAR ADC with decision time quantization based redundancy |
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