Enhance hardware security using FIFO in pipelines

Cryptographic functions are foundation of many information security applications. Embedded cryptographic hardware is vulnerable to side channel attacks such as power analysis- and fault- attacks. In this paper, we propose a design architecture which enhances the hardware security against such attack...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kuan Jen Lin, Chih Ping Weng, Tsai Kun Hou
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	AES Clocks Cryptographic hardware Cryptography DPA attack Hardware Pipeline processing Pipelines Power demand Registers Temporal jitter
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