Design of new full adder cell using hybrid-CMOS logic style
In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of...
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| creator | Zavarei, M. J. Baghbanmanesh, M. R. Kargaran, E. Nabovati, H. Golmakani, A. |
| description | In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits. |
| doi_str_mv | 10.1109/ICECS.2011.6122310 |
| format | Conference Proceeding |
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| language | eng |
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| subjects | Adders CMOS integrated circuits Delay Integrated circuit modeling Power dissipation Simulation Transistors |
| title | Design of new full adder cell using hybrid-CMOS logic style |
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