Load-Aware Dynamic Partial Reconfiguration Implementation of Crossbar Scheduler

FPGA dynamic partial reconfiguration (DPR) tend to be adopted for its flexibility and fewer resource consumption increasingly in hardware implementation, especially in communication devices. A crossbar scheduling algorithm is used to schedule the crossbar, or decide the order in which cells will be served. The is lip and FIRM are two classic crossbar scheduling algorithms, but they do not support DPR. Performance of these two algorithms differs under varying workloads (load: cells' arrival speed). With the development of DPR, implementations of these algorithms will have improvement both in performance and resource usage. DPR reduces 7.249% average delay than iSlip does and 0.013% average delay than FIRM does in 4×4 crossbar. It reduces 17.9% average delay than iSlip does and 0.039% average delay than FIRM does in 8×8 crossbar. In this paper, we compared the DPR implementation and non-DPR implementations (iSlip and FIRM) and found that the former reduces 37.744% LUTs and 47.874% FFs in 4×4 crossbar, and 47.325% LUTs and 49.907% FFs in 8×8 crossbar.