Package design optimization for efficient on-chip-capacitance leveraging

This paper focuses on the power delivery network (PDN) characterization of high speed IC; particularly focusing on the on-chip capacitance (Cdie). Three packages were used to examine how Cdie would vary when selected power rails were merged on package. The first package carries isolated power rails...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Fern Nee Tan, Sheng Chyan Lee, Faidz, Abd Rahman
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitance Core logic Electrical resistance measurement impedance profile (Z-profile) Input-Output buffers (I/O buffers) On-chip capacitance (Cdie) power delivery network (PDN) Probes Rails Resistance Silicon Substrates Vector Network Analyzer (VNA)
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