Characteristics of 0.1 /spl mu/m Si MOSFETs with ISRC (Inverted-Sidewall Recessed-Channel) structure for reduced short channel effect

To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quarter-micrometer MOSFETs, we have fabricated a 0.1 /spl mu/m recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel) and verified its superiority. The oxide thickne...

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Hauptverfasser:	Jeongho Lyu, Youngjin Choi, Yeong Taek Lee, Byung-Gook Park, Kukjin Chun, Jong Duk Lee
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit simulation Electric variables Etching High speed optical techniques Hot carriers Lithography MOSFETs Optical device fabrication Oxidation Threshold voltage
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creator	Jeongho Lyu Youngjin Choi Yeong Taek Lee Byung-Gook Park Kukjin Chun Jong Duk Lee
description	To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quarter-micrometer MOSFETs, we have fabricated a 0.1 /spl mu/m recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel) and verified its superiority. The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m. The maximum transconductance at V/sub D/=2.0 V is 455 mS/mm for nMOSFET and 191 mS/mm for pMOSFET. The DIBL (Drain Induced Barrier Lowering) is kept within 70 mV from V/sub D/=0.1 V to V/sub D/=2.0 V for both devices. By the comparison with the conventional MOSFET, the reduction of short channel effects is demonstrated. By simulation, it is verified that this results from the laterally non-uniformly doped channel profile.
doi_str_mv	10.1109/COMMAD.1996.610107
format	Conference Proceeding
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The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m. The maximum transconductance at V/sub D/=2.0 V is 455 mS/mm for nMOSFET and 191 mS/mm for pMOSFET. The DIBL (Drain Induced Barrier Lowering) is kept within 70 mV from V/sub D/=0.1 V to V/sub D/=2.0 V for both devices. By the comparison with the conventional MOSFET, the reduction of short channel effects is demonstrated. By simulation, it is verified that this results from the laterally non-uniformly doped channel profile.</description><identifier>ISBN: 0780333748</identifier><identifier>ISBN: 9780780333741</identifier><identifier>DOI: 10.1109/COMMAD.1996.610107</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; Electric variables ; Etching ; High speed optical techniques ; Hot carriers ; Lithography ; MOSFETs ; Optical device fabrication ; Oxidation ; Threshold voltage</subject><ispartof>1996 Conference on Optoelectronic and Microelectronic Materials and Devices. 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language	eng
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subjects	Circuit simulation Electric variables Etching High speed optical techniques Hot carriers Lithography MOSFETs Optical device fabrication Oxidation Threshold voltage
title	Characteristics of 0.1 /spl mu/m Si MOSFETs with ISRC (Inverted-Sidewall Recessed-Channel) structure for reduced short channel effect
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