Improvement in reliability by changing the deterministic inputs of nanoscale circuits

Improvement in reliability by changing the deterministic inputs of nanoscale circuits

Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuit's reliability due to the circuit's internal noises and gate errors. In this paper, we will mod...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Khalid, U., Anwer, J., Singh, N., Hamid, N. H., Asirvadam, V. S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bayesian methods
Bayesian networks
deterministic Inputs
Integrated circuit modeling
Integrated circuit reliability
Logic gates
Nanoscale devices
reliability
Reliability engineering
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 197
container_issue
container_start_page 195
container_title
container_volume
creator Khalid, U.
Anwer, J.
Singh, N.
Hamid, N. H.
Asirvadam, V. S.
description Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuit's reliability due to the circuit's internal noises and gate errors. In this paper, we will model the deterministic inputs probabilistically and analyze their effect on the reliability of digital circuits. The analysis is based on the Bayesian networks error modelling scheme. The simulations are based on MATLAB and show the important relationships among different deterministic inputs and their reliabilities. The results show the range of reliability values obtained by changing the deterministic input probability values.
doi_str_mv 10.1109/RSM.2011.6088322
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6088322</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6088322</ieee_id><sourcerecordid>6088322</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-c5e133435920fd24435a1f9a54d21018f57498d692b66f1b7ae4ae86ad684eb23</originalsourceid><addsrcrecordid>eNo1kEFLAzEUhCMiqLV3wUv-wNa8JJtNjlLUFiqC1nPJ7r5tn-ymJUmF_nsXrHMZBj6GYRi7BzEDEO7x4_NtJgXAzAhrlZQXbOoqCwak1VaX1SW7_Q9aXbNpSt9ilDHOKbhhX8vhEPc_OGDInAKP2JOvqad84vWJNzsfthS2PO-Qt5gxDhQoZWpG-HDMie87HnzYp8b3yBuKzZFyumNXne8TTs8-YeuX5_V8UazeX5fzp1VBTuSiKRGU0qp0UnStHPeVHjrnS91KEGC7stLOtsbJ2pgO6sqj9miNb43VWEs1YQ9_tYSIm0OkwcfT5nyE-gUoRFIW</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Improvement in reliability by changing the deterministic inputs of nanoscale circuits</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Khalid, U. ; Anwer, J. ; Singh, N. ; Hamid, N. H. ; Asirvadam, V. S.</creator><creatorcontrib>Khalid, U. ; Anwer, J. ; Singh, N. ; Hamid, N. H. ; Asirvadam, V. S.</creatorcontrib><description>Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuit's reliability due to the circuit's internal noises and gate errors. In this paper, we will model the deterministic inputs probabilistically and analyze their effect on the reliability of digital circuits. The analysis is based on the Bayesian networks error modelling scheme. The simulations are based on MATLAB and show the important relationships among different deterministic inputs and their reliabilities. The results show the range of reliability values obtained by changing the deterministic input probability values.</description><identifier>ISBN: 1612848443</identifier><identifier>ISBN: 9781612848440</identifier><identifier>EISBN: 9781612848457</identifier><identifier>EISBN: 9781612848464</identifier><identifier>EISBN: 161284846X</identifier><identifier>EISBN: 1612848451</identifier><identifier>DOI: 10.1109/RSM.2011.6088322</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bayesian methods ; Bayesian networks ; deterministic Inputs ; Integrated circuit modeling ; Integrated circuit reliability ; Logic gates ; Nanoscale devices ; reliability ; Reliability engineering</subject><ispartof>2011 IEEE Regional Symposium on Micro and Nano Electronics, 2011, p.195-197</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6088322$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6088322$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Khalid, U.</creatorcontrib><creatorcontrib>Anwer, J.</creatorcontrib><creatorcontrib>Singh, N.</creatorcontrib><creatorcontrib>Hamid, N. H.</creatorcontrib><creatorcontrib>Asirvadam, V. S.</creatorcontrib><title>Improvement in reliability by changing the deterministic inputs of nanoscale circuits</title><title>2011 IEEE Regional Symposium on Micro and Nano Electronics</title><addtitle>RSM</addtitle><description>Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuit's reliability due to the circuit's internal noises and gate errors. In this paper, we will model the deterministic inputs probabilistically and analyze their effect on the reliability of digital circuits. The analysis is based on the Bayesian networks error modelling scheme. The simulations are based on MATLAB and show the important relationships among different deterministic inputs and their reliabilities. The results show the range of reliability values obtained by changing the deterministic input probability values.</description><subject>Bayesian methods</subject><subject>Bayesian networks</subject><subject>deterministic Inputs</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuit reliability</subject><subject>Logic gates</subject><subject>Nanoscale devices</subject><subject>reliability</subject><subject>Reliability engineering</subject><isbn>1612848443</isbn><isbn>9781612848440</isbn><isbn>9781612848457</isbn><isbn>9781612848464</isbn><isbn>161284846X</isbn><isbn>1612848451</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kEFLAzEUhCMiqLV3wUv-wNa8JJtNjlLUFiqC1nPJ7r5tn-ymJUmF_nsXrHMZBj6GYRi7BzEDEO7x4_NtJgXAzAhrlZQXbOoqCwak1VaX1SW7_Q9aXbNpSt9ilDHOKbhhX8vhEPc_OGDInAKP2JOvqad84vWJNzsfthS2PO-Qt5gxDhQoZWpG-HDMie87HnzYp8b3yBuKzZFyumNXne8TTs8-YeuX5_V8UazeX5fzp1VBTuSiKRGU0qp0UnStHPeVHjrnS91KEGC7stLOtsbJ2pgO6sqj9miNb43VWEs1YQ9_tYSIm0OkwcfT5nyE-gUoRFIW</recordid><startdate>201109</startdate><enddate>201109</enddate><creator>Khalid, U.</creator><creator>Anwer, J.</creator><creator>Singh, N.</creator><creator>Hamid, N. H.</creator><creator>Asirvadam, V. S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201109</creationdate><title>Improvement in reliability by changing the deterministic inputs of nanoscale circuits</title><author>Khalid, U. ; Anwer, J. ; Singh, N. ; Hamid, N. H. ; Asirvadam, V. S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-c5e133435920fd24435a1f9a54d21018f57498d692b66f1b7ae4ae86ad684eb23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Bayesian methods</topic><topic>Bayesian networks</topic><topic>deterministic Inputs</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuit reliability</topic><topic>Logic gates</topic><topic>Nanoscale devices</topic><topic>reliability</topic><topic>Reliability engineering</topic><toplevel>online_resources</toplevel><creatorcontrib>Khalid, U.</creatorcontrib><creatorcontrib>Anwer, J.</creatorcontrib><creatorcontrib>Singh, N.</creatorcontrib><creatorcontrib>Hamid, N. H.</creatorcontrib><creatorcontrib>Asirvadam, V. S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Khalid, U.</au><au>Anwer, J.</au><au>Singh, N.</au><au>Hamid, N. H.</au><au>Asirvadam, V. S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Improvement in reliability by changing the deterministic inputs of nanoscale circuits</atitle><btitle>2011 IEEE Regional Symposium on Micro and Nano Electronics</btitle><stitle>RSM</stitle><date>2011-09</date><risdate>2011</risdate><spage>195</spage><epage>197</epage><pages>195-197</pages><isbn>1612848443</isbn><isbn>9781612848440</isbn><eisbn>9781612848457</eisbn><eisbn>9781612848464</eisbn><eisbn>161284846X</eisbn><eisbn>1612848451</eisbn><abstract>Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuit's reliability due to the circuit's internal noises and gate errors. In this paper, we will model the deterministic inputs probabilistically and analyze their effect on the reliability of digital circuits. The analysis is based on the Bayesian networks error modelling scheme. The simulations are based on MATLAB and show the important relationships among different deterministic inputs and their reliabilities. The results show the range of reliability values obtained by changing the deterministic input probability values.</abstract><pub>IEEE</pub><doi>10.1109/RSM.2011.6088322</doi><tpages>3</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1612848443
ispartof 2011 IEEE Regional Symposium on Micro and Nano Electronics, 2011, p.195-197
issn
language eng
recordid cdi_ieee_primary_6088322
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bayesian methods
Bayesian networks
deterministic Inputs
Integrated circuit modeling
Integrated circuit reliability
Logic gates
Nanoscale devices
reliability
Reliability engineering
title Improvement in reliability by changing the deterministic inputs of nanoscale circuits
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T01%3A36%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Improvement%20in%20reliability%20by%20changing%20the%20deterministic%20inputs%20of%20nanoscale%20circuits&rft.btitle=2011%20IEEE%20Regional%20Symposium%20on%20Micro%20and%20Nano%20Electronics&rft.au=Khalid,%20U.&rft.date=2011-09&rft.spage=195&rft.epage=197&rft.pages=195-197&rft.isbn=1612848443&rft.isbn_list=9781612848440&rft_id=info:doi/10.1109/RSM.2011.6088322&rft_dat=%3Cieee_6IE%3E6088322%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781612848457&rft.eisbn_list=9781612848464&rft.eisbn_list=161284846X&rft.eisbn_list=1612848451&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6088322&rfr_iscdi=true