A multi-segment clocking scheme to reduce on-chip EMI

This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the c...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mesgarzadeh, B., Zadeh, I. E., Alvandpour, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	clock clock distribution Clocks CMOS Electromagnetic interference Electromagnetic radiation EMI Harmonic analysis Power dissipation Power system harmonics short circuit power System-on-a-chip TECHNOLOGY TEKNIKVETENSKAP
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