A multi-segment clocking scheme to reduce on-chip EMI
This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the c...
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| creator | Mesgarzadeh, B. Zadeh, I. E. Alvandpour, A. |
| description | This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction. |
| doi_str_mv | 10.1109/SOCC.2011.6085110 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>swepub_6IE</sourceid><recordid>TN_cdi_ieee_primary_6085110</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6085110</ieee_id><sourcerecordid>oai_DiVA_org_liu_65492</sourcerecordid><originalsourceid>FETCH-LOGICAL-i212t-789809f85e2134ca620d89a1176e9705f94a912224520c02b292abfba9a6a7f53</originalsourceid><addsrcrecordid>eNpVkMtOwzAURM1Loir9AMTGH0CK7619bS-rUKBSURc8tpHjOq0haao8hPh7KrUgMZuRZo5mMYxdgxgDCHv3skzTMQqAMQmj9tEJG1ltQCqtgUDDKRsgkExACzr715E8_-1I0yUbte2H2IvIGhIDpqa86ssuJm1YV2HbcV_W_jNu17z1m1AF3tW8CaveB15vE7-JOz57nl-xi8KVbRgdfcjeHmav6VOyWD7O0-kiiQjYJdpYI2xhVECYSO8IxcpYB6ApWC1UYaWzgIhSofACc7To8iJ31pHThZoM2e1ht_0Kuz7Pdk2sXPOd1S5m9_F9mtXNOitjn5GSFvf4zQGPIYQ_-PjZ5AcJYFiS</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A multi-segment clocking scheme to reduce on-chip EMI</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Mesgarzadeh, B. ; Zadeh, I. E. ; Alvandpour, A.</creator><creatorcontrib>Mesgarzadeh, B. ; Zadeh, I. E. ; Alvandpour, A.</creatorcontrib><description>This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.</description><identifier>ISSN: 2164-1676</identifier><identifier>ISBN: 9781457716164</identifier><identifier>ISBN: 145771616X</identifier><identifier>EISSN: 2164-1706</identifier><identifier>EISBN: 9781457716171</identifier><identifier>EISBN: 9781457716157</identifier><identifier>EISBN: 1457716178</identifier><identifier>EISBN: 1457716151</identifier><identifier>DOI: 10.1109/SOCC.2011.6085110</identifier><language>eng</language><publisher>IEEE</publisher><subject>clock ; clock distribution ; Clocks ; CMOS ; Electromagnetic interference ; Electromagnetic radiation ; EMI ; Harmonic analysis ; Power dissipation ; Power system harmonics ; short circuit power ; System-on-a-chip ; TECHNOLOGY ; TEKNIKVETENSKAP</subject><ispartof>2011 IEEE International SOC Conference, 2011, p.251-255</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6085110$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,885,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6085110$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-65492$$DView record from Swedish Publication Index$$Hfree_for_read</backlink></links><search><creatorcontrib>Mesgarzadeh, B.</creatorcontrib><creatorcontrib>Zadeh, I. E.</creatorcontrib><creatorcontrib>Alvandpour, A.</creatorcontrib><title>A multi-segment clocking scheme to reduce on-chip EMI</title><title>2011 IEEE International SOC Conference</title><addtitle>SOCC</addtitle><description>This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.</description><subject>clock</subject><subject>clock distribution</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Electromagnetic interference</subject><subject>Electromagnetic radiation</subject><subject>EMI</subject><subject>Harmonic analysis</subject><subject>Power dissipation</subject><subject>Power system harmonics</subject><subject>short circuit power</subject><subject>System-on-a-chip</subject><subject>TECHNOLOGY</subject><subject>TEKNIKVETENSKAP</subject><issn>2164-1676</issn><issn>2164-1706</issn><isbn>9781457716164</isbn><isbn>145771616X</isbn><isbn>9781457716171</isbn><isbn>9781457716157</isbn><isbn>1457716178</isbn><isbn>1457716151</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtOwzAURM1Loir9AMTGH0CK7619bS-rUKBSURc8tpHjOq0haao8hPh7KrUgMZuRZo5mMYxdgxgDCHv3skzTMQqAMQmj9tEJG1ltQCqtgUDDKRsgkExACzr715E8_-1I0yUbte2H2IvIGhIDpqa86ssuJm1YV2HbcV_W_jNu17z1m1AF3tW8CaveB15vE7-JOz57nl-xi8KVbRgdfcjeHmav6VOyWD7O0-kiiQjYJdpYI2xhVECYSO8IxcpYB6ApWC1UYaWzgIhSofACc7To8iJ31pHThZoM2e1ht_0Kuz7Pdk2sXPOd1S5m9_F9mtXNOitjn5GSFvf4zQGPIYQ_-PjZ5AcJYFiS</recordid><startdate>201109</startdate><enddate>201109</enddate><creator>Mesgarzadeh, B.</creator><creator>Zadeh, I. E.</creator><creator>Alvandpour, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>ADTPV</scope><scope>BNKNJ</scope><scope>DG8</scope></search><sort><creationdate>201109</creationdate><title>A multi-segment clocking scheme to reduce on-chip EMI</title><author>Mesgarzadeh, B. ; Zadeh, I. E. ; Alvandpour, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i212t-789809f85e2134ca620d89a1176e9705f94a912224520c02b292abfba9a6a7f53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>clock</topic><topic>clock distribution</topic><topic>Clocks</topic><topic>CMOS</topic><topic>Electromagnetic interference</topic><topic>Electromagnetic radiation</topic><topic>EMI</topic><topic>Harmonic analysis</topic><topic>Power dissipation</topic><topic>Power system harmonics</topic><topic>short circuit power</topic><topic>System-on-a-chip</topic><topic>TECHNOLOGY</topic><topic>TEKNIKVETENSKAP</topic><toplevel>online_resources</toplevel><creatorcontrib>Mesgarzadeh, B.</creatorcontrib><creatorcontrib>Zadeh, I. E.</creatorcontrib><creatorcontrib>Alvandpour, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEL</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>SwePub</collection><collection>SwePub Conference</collection><collection>SWEPUB Linköpings universitet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mesgarzadeh, B.</au><au>Zadeh, I. E.</au><au>Alvandpour, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A multi-segment clocking scheme to reduce on-chip EMI</atitle><btitle>2011 IEEE International SOC Conference</btitle><stitle>SOCC</stitle><date>2011-09</date><risdate>2011</risdate><spage>251</spage><epage>255</epage><pages>251-255</pages><issn>2164-1676</issn><eissn>2164-1706</eissn><isbn>9781457716164</isbn><isbn>145771616X</isbn><eisbn>9781457716171</eisbn><eisbn>9781457716157</eisbn><eisbn>1457716178</eisbn><eisbn>1457716151</eisbn><abstract>This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.</abstract><pub>IEEE</pub><doi>10.1109/SOCC.2011.6085110</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2164-1676 |
| ispartof | 2011 IEEE International SOC Conference, 2011, p.251-255 |
| issn | 2164-1676 2164-1706 |
| language | eng |
| recordid | cdi_ieee_primary_6085110 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | clock clock distribution Clocks CMOS Electromagnetic interference Electromagnetic radiation EMI Harmonic analysis Power dissipation Power system harmonics short circuit power System-on-a-chip TECHNOLOGY TEKNIKVETENSKAP |
| title | A multi-segment clocking scheme to reduce on-chip EMI |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T16%3A13%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-swepub_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20multi-segment%20clocking%20scheme%20to%20reduce%20on-chip%20EMI&rft.btitle=2011%20IEEE%20International%20SOC%20Conference&rft.au=Mesgarzadeh,%20B.&rft.date=2011-09&rft.spage=251&rft.epage=255&rft.pages=251-255&rft.issn=2164-1676&rft.eissn=2164-1706&rft.isbn=9781457716164&rft.isbn_list=145771616X&rft_id=info:doi/10.1109/SOCC.2011.6085110&rft_dat=%3Cswepub_6IE%3Eoai_DiVA_org_liu_65492%3C/swepub_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781457716171&rft.eisbn_list=9781457716157&rft.eisbn_list=1457716178&rft.eisbn_list=1457716151&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6085110&rfr_iscdi=true |