Impact and optimization of lithography-aware regular layout in digital circuit design
Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular...
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| creator | Dal Bem, V. Butzen, P. Marranghello, F. S. Reis, A. I. Ribas, R. P. |
| description | Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template. |
| doi_str_mv | 10.1109/ICCD.2011.6081409 |
| format | Conference Proceeding |
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Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.</description><subject>Benchmark testing</subject><subject>CMOS digital circuits</subject><subject>Fabrics</subject><subject>Layout</subject><subject>layout pattern optimization</subject><subject>Libraries</subject><subject>lithography-aware design</subject><subject>Logic gates</subject><subject>Optimization</subject><subject>regular fabric</subject><subject>standard cells</subject><subject>structured ASIC</subject><subject>Transistor regular layout</subject><subject>Transistors</subject><issn>1063-6404</issn><issn>2576-6996</issn><isbn>9781457719530</isbn><isbn>1457719533</isbn><isbn>9781457719547</isbn><isbn>1457719541</isbn><isbn>9781457719523</isbn><isbn>1457719525</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtqwzAURNUXNKT5gNKNfsCprt5aFvcVCHSTrsO1LDsqjm1khZJ-fQPNprOZAwNnMYTcA1sCMPe4KsvnJWcAS80sSOYuyMKZEyljwClpLsmMK6ML7Zy--rcJdk1mwLQotGTyliym6YudorW1zszI52o_os8U-5oOY477-IM5Dj0dGtrFvBvahOPuWOA3pkBTaA8dJtrhcThkGntaxzZm7KiPyR9ipnWYYtvfkZsGuykszj0nm9eXTflerD_eVuXTuoiO5UIpVByqKkgpKmcar7z1EgSzzEhwvLFYV7yyNqBxjAfLnfAeoNZSNAKVmJOHP20MIWzHFPeYjtvzR-IXrjVWkQ</recordid><startdate>201110</startdate><enddate>201110</enddate><creator>Dal Bem, V.</creator><creator>Butzen, P.</creator><creator>Marranghello, F. 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P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Impact and optimization of lithography-aware regular layout in digital circuit design</atitle><btitle>2011 IEEE 29th International Conference on Computer Design (ICCD)</btitle><stitle>ICCD</stitle><date>2011-10</date><risdate>2011</risdate><spage>279</spage><epage>284</epage><pages>279-284</pages><issn>1063-6404</issn><eissn>2576-6996</eissn><isbn>9781457719530</isbn><isbn>1457719533</isbn><eisbn>9781457719547</eisbn><eisbn>1457719541</eisbn><eisbn>9781457719523</eisbn><eisbn>1457719525</eisbn><abstract>Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.</abstract><pub>IEEE</pub><doi>10.1109/ICCD.2011.6081409</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1063-6404 |
| ispartof | 2011 IEEE 29th International Conference on Computer Design (ICCD), 2011, p.279-284 |
| issn | 1063-6404 2576-6996 |
| language | eng |
| recordid | cdi_ieee_primary_6081409 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Benchmark testing CMOS digital circuits Fabrics Layout layout pattern optimization Libraries lithography-aware design Logic gates Optimization regular fabric standard cells structured ASIC Transistor regular layout Transistors |
| title | Impact and optimization of lithography-aware regular layout in digital circuit design |
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