32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches
Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track stru...
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| Veröffentlicht in: | IEEE transactions on nuclear science 2011-12, Vol.58 (6), p.2702-2710 |
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| container_title | IEEE transactions on nuclear science |
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| creator | Rodbell, K. P. Heidel, D. F. Pellish, J. A. Marshall, P. W. Tang, H. H. K. Murray, C. E. LaBel, K. A. Gordon, M. S. Stawiasz, K. G. Schwank, J. R. Berg, M. D. Kim, H. S. Friendlich, M. R. Phan, A. M. Seidleck, C. M. |
| description | Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts. |
| doi_str_mv | 10.1109/TNS.2011.2171715 |
| format | Article |
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P. ; Heidel, D. F. ; Pellish, J. A. ; Marshall, P. W. ; Tang, H. H. K. ; Murray, C. E. ; LaBel, K. A. ; Gordon, M. S. ; Stawiasz, K. G. ; Schwank, J. R. ; Berg, M. D. ; Kim, H. S. ; Friendlich, M. R. ; Phan, A. M. ; Seidleck, C. M.</creator><creatorcontrib>Rodbell, K. P. ; Heidel, D. F. ; Pellish, J. A. ; Marshall, P. W. ; Tang, H. H. K. ; Murray, C. E. ; LaBel, K. A. ; Gordon, M. S. ; Stawiasz, K. G. ; Schwank, J. R. ; Berg, M. D. ; Kim, H. S. ; Friendlich, M. R. ; Phan, A. M. ; Seidleck, C. M.</creatorcontrib><description>Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.2011.2171715</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>32 nm and 45 nm SOI hardened latches ; angle dependent cross-section distributions ; CMOS ; Computer simulation ; Cross sections ; Data processing ; heavy ion modeling ; Latches ; Mathematical models ; Monte Carlo methods ; Protons ; Radiation hardening ; sensitive node separation ; Silicon on insulator technology ; silicon-on-insulator technology (SOI) ; single event effects (SEE) ; Single event upset ; single event upset (SEU) ; Single event upsets ; track structures</subject><ispartof>IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.2702-2710</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Dec 2011</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c389t-a9e5bda80e625c1482bdf54169f2d04a3d9b36bda217cd17e2a00c18078efaa43</citedby><cites>FETCH-LOGICAL-c389t-a9e5bda80e625c1482bdf54169f2d04a3d9b36bda217cd17e2a00c18078efaa43</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6078448$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6078448$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Rodbell, K. P.</creatorcontrib><creatorcontrib>Heidel, D. F.</creatorcontrib><creatorcontrib>Pellish, J. A.</creatorcontrib><creatorcontrib>Marshall, P. W.</creatorcontrib><creatorcontrib>Tang, H. H. K.</creatorcontrib><creatorcontrib>Murray, C. E.</creatorcontrib><creatorcontrib>LaBel, K. A.</creatorcontrib><creatorcontrib>Gordon, M. S.</creatorcontrib><creatorcontrib>Stawiasz, K. G.</creatorcontrib><creatorcontrib>Schwank, J. R.</creatorcontrib><creatorcontrib>Berg, M. D.</creatorcontrib><creatorcontrib>Kim, H. S.</creatorcontrib><creatorcontrib>Friendlich, M. R.</creatorcontrib><creatorcontrib>Phan, A. M.</creatorcontrib><creatorcontrib>Seidleck, C. M.</creatorcontrib><title>32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches</title><title>IEEE transactions on nuclear science</title><addtitle>TNS</addtitle><description>Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. 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It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.</description><subject>32 nm and 45 nm SOI hardened latches</subject><subject>angle dependent cross-section distributions</subject><subject>CMOS</subject><subject>Computer simulation</subject><subject>Cross sections</subject><subject>Data processing</subject><subject>heavy ion modeling</subject><subject>Latches</subject><subject>Mathematical models</subject><subject>Monte Carlo methods</subject><subject>Protons</subject><subject>Radiation hardening</subject><subject>sensitive node separation</subject><subject>Silicon on insulator technology</subject><subject>silicon-on-insulator technology (SOI)</subject><subject>single event effects (SEE)</subject><subject>Single event upset</subject><subject>single event upset (SEU)</subject><subject>Single event upsets</subject><subject>track structures</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkMFLwzAUh4MoOKd3wUvxNA-ZeWnSJuBFN3WD4WCb55A2r9rRtbPpDvvvzdjwIO_wePD9Hj8-Qm6BDQGYflx9LIecAQw5pGHkGemBlIqCTNU56TEGimqh9SW58n4dTiGZ7JGnmEe2dpGQUb2JFtaVtiubmk5s67BGR7M9HaMvv-posJi8jB-i5XwazWyXf6O_JheFrTzenHaffL69rkYTOpu_T0fPM5rHSnfUapSZs4phwmUOQvHMFVJAogvumLCx01mcBCJUzx2kyC1jOSiWKiysFXGfDI5_t23zs0PfmU3pc6wqW2Oz8wYYMKWEEDyg9__QdbNr69DOaBAilSJNAsSOUN423rdYmG1bbmy7D5_MwaYJNs3BpjnZDJG7Y6RExD88CRWFUPEvKzxsUQ</recordid><startdate>201112</startdate><enddate>201112</enddate><creator>Rodbell, K. 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P.</au><au>Heidel, D. F.</au><au>Pellish, J. A.</au><au>Marshall, P. W.</au><au>Tang, H. H. K.</au><au>Murray, C. E.</au><au>LaBel, K. A.</au><au>Gordon, M. S.</au><au>Stawiasz, K. G.</au><au>Schwank, J. R.</au><au>Berg, M. D.</au><au>Kim, H. S.</au><au>Friendlich, M. R.</au><au>Phan, A. M.</au><au>Seidleck, C. M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches</atitle><jtitle>IEEE transactions on nuclear science</jtitle><stitle>TNS</stitle><date>2011-12</date><risdate>2011</risdate><volume>58</volume><issue>6</issue><spage>2702</spage><epage>2710</epage><pages>2702-2710</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNS.2011.2171715</doi><tpages>9</tpages></addata></record> |
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| subjects | 32 nm and 45 nm SOI hardened latches angle dependent cross-section distributions CMOS Computer simulation Cross sections Data processing heavy ion modeling Latches Mathematical models Monte Carlo methods Protons Radiation hardening sensitive node separation Silicon on insulator technology silicon-on-insulator technology (SOI) single event effects (SEE) Single event upset single event upset (SEU) Single event upsets track structures |
| title | 32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches |
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