A generic execution model for efficient performance evaluation of system architectures at transaction level
Models are necessary to assist system architects in evaluating performances of hardware/software architectures and performing early exploration of the design space. Efficient modeling approaches are then required to cope with the still increasing complexity of embedded systems. In this paper, we pre...
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| creator | Le Nours, S. Barreteau, A. Pasquier, O. |
| description | Models are necessary to assist system architects in evaluating performances of hardware/software architectures and performing early exploration of the design space. Efficient modeling approaches are then required to cope with the still increasing complexity of embedded systems. In this paper, we present a generic execution model to favor creation of transaction level models for performance evaluation and architecture exploration. Based on this generic model, the created models are used to evaluate by simulation expected processing and memory resources related to system architectures. The benefits of the proposed approach are highlighted through the analysis of an heterogeneous architecture implementing the reception part of the physical layer of the LTE protocol. |
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The benefits of the proposed approach are highlighted through the analysis of an heterogeneous architecture implementing the reception part of the physical layer of the LTE protocol.</description><identifier>ISSN: 1636-9874</identifier><identifier>ISBN: 9781457707636</identifier><identifier>ISBN: 1457707632</identifier><identifier>EISBN: 9782953050448</identifier><identifier>EISBN: 2953050434</identifier><identifier>EISBN: 2953050442</identifier><identifier>EISBN: 9782953050431</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; architecture modeling ; Computational modeling ; Computer architecture ; Data models ; Load modeling ; Performance evaluation ; transaction level modeling ; Unified modeling language</subject><ispartof>FDL 2011 Proceedings, 2011, p.1-8</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6069476$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6069476$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Le Nours, S.</creatorcontrib><creatorcontrib>Barreteau, A.</creatorcontrib><creatorcontrib>Pasquier, O.</creatorcontrib><title>A generic execution model for efficient performance evaluation of system architectures at transaction level</title><title>FDL 2011 Proceedings</title><addtitle>FDL</addtitle><description>Models are necessary to assist system architects in evaluating performances of hardware/software architectures and performing early exploration of the design space. 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The benefits of the proposed approach are highlighted through the analysis of an heterogeneous architecture implementing the reception part of the physical layer of the LTE protocol.</description><subject>Analytical models</subject><subject>architecture modeling</subject><subject>Computational modeling</subject><subject>Computer architecture</subject><subject>Data models</subject><subject>Load modeling</subject><subject>Performance evaluation</subject><subject>transaction level modeling</subject><subject>Unified modeling language</subject><issn>1636-9874</issn><isbn>9781457707636</isbn><isbn>1457707632</isbn><isbn>9782953050448</isbn><isbn>2953050434</isbn><isbn>2953050442</isbn><isbn>9782953050431</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jkFqwzAURFWSQkPiE3TzLxCQY1myl6W09ADZh48yStXKcpDk0Ny-xnTd1WNm3mIeRNWb7tC3jWylUt1qybVqjZFGN3otNvWMfd8Z9SSqnL-klLXRulHtRny_0AURyVvCD-xU_BhpGM8I5MZEcM5bj1joijQXA0cLwo3DxIs6Osr3XDAQJ_vpC2yZEjJxoZI4ZraLFnBD2IlHxyGj-uNWPL-_HV8_9h7A6Zr8wOl-0lL3aj7-__oLMSRJ4Q</recordid><startdate>201109</startdate><enddate>201109</enddate><creator>Le Nours, S.</creator><creator>Barreteau, A.</creator><creator>Pasquier, O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201109</creationdate><title>A generic execution model for efficient performance evaluation of system architectures at transaction level</title><author>Le Nours, S. ; Barreteau, A. ; Pasquier, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_60694763</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Analytical models</topic><topic>architecture modeling</topic><topic>Computational modeling</topic><topic>Computer architecture</topic><topic>Data models</topic><topic>Load modeling</topic><topic>Performance evaluation</topic><topic>transaction level modeling</topic><topic>Unified modeling language</topic><toplevel>online_resources</toplevel><creatorcontrib>Le Nours, S.</creatorcontrib><creatorcontrib>Barreteau, A.</creatorcontrib><creatorcontrib>Pasquier, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Le Nours, S.</au><au>Barreteau, A.</au><au>Pasquier, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A generic execution model for efficient performance evaluation of system architectures at transaction level</atitle><btitle>FDL 2011 Proceedings</btitle><stitle>FDL</stitle><date>2011-09</date><risdate>2011</risdate><spage>1</spage><epage>8</epage><pages>1-8</pages><issn>1636-9874</issn><isbn>9781457707636</isbn><isbn>1457707632</isbn><eisbn>9782953050448</eisbn><eisbn>2953050434</eisbn><eisbn>2953050442</eisbn><eisbn>9782953050431</eisbn><abstract>Models are necessary to assist system architects in evaluating performances of hardware/software architectures and performing early exploration of the design space. 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| ispartof | FDL 2011 Proceedings, 2011, p.1-8 |
| issn | 1636-9874 |
| language | eng |
| recordid | cdi_ieee_primary_6069476 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analytical models architecture modeling Computational modeling Computer architecture Data models Load modeling Performance evaluation transaction level modeling Unified modeling language |
| title | A generic execution model for efficient performance evaluation of system architectures at transaction level |
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