Large dynamic range high resolution digital delay generator based on FPGA

A novel digital delay generator (DDG) based on FPGA was designed with 4.4ms range and 65ps resolution. The time-to- digital conversion (TDC) utilizing dual tapped delay lines was implemented in the FPGA to accurately measure the time interval between the rising edge of the FPGA global clock and the...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yan Song, Hao Liang, Lei Zhou, Jiye Du, Jiming Ma, Zhiqin Yue
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	AD9501 Built-in self-test Clocks Delay Delay lines Digital Delay Generator Field programmable gate arrays FPGA Generators Signal resolution TDC
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