IO buffer for high performance, low-power application

An IO buffer architecture is shown which provides fast output transitions as well as efficient voltage level shifting from the chip interior. The buffer contains a feedback circuit which damps ringing associated with supply bounce. Fast voltage converters are demonstrated which allow the core to ope...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Shor, J.S., Afek, Y., Engel, E.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitance CMOS logic circuits CMOS technology Delay Digital signal processing Feedback circuits Inverters Pins Switches Voltage
Online-Zugang:	Volltext bestellen
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