Wire sweep study for SOT package array matrix molding with simulation and experimental analysis

Small Outline Transistor (SOT) packages, widely used in consumer electronics, are very small, inexpensive surface-mount plastic molded packages. In order to maximize product throughput, the molded array matrix is employed for products fabrication, which leads to a potential critical wire sweep issue...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Jiale Han, Haibin Chen, Ke Xue, Fei Wong, Leung, K., Shiu, I., Jingshen Wu
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analytical models Arrays Mathematical model Three dimensional displays Transfer molding Viscosity Wires
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