Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution
Feature matching is an indispensable process for object recognition, which is an important issue for wearable devices with video analysis functionalities. To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP) is employed to accelerate the speed of featur...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2012-12, Vol.20 (12), p.2329-2332 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | CHEN, Tse-Wei SU, Yu-Chi HUANG, Keng-Yen TSAI, Yi-Min CHIEN, Shao-Yi CHEN, Liang-Gee |
| description | Feature matching is an indispensable process for object recognition, which is an important issue for wearable devices with video analysis functionalities. To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP) is employed to accelerate the speed of feature matching. The VVP can transform hundreds of 128-D SIFT vectors into a 64-D histogram for object matching by using the binary-tree-based architecture, and 16 calculators for the computations of the Euclidean distances are designed for each of the two processors in each level. A total of 126 visual words can be saved in the six-level hierarchical memory, which instantly offers the data required for the matching process, and more than 5 times of bandwidth can be saved compared with the non-binary-tree-based architecture. As a part of the recognition SoC, the VVP is implemented with the 65-nm CMOS technology, and the experimental results show that the gate count and the average power consumption are 280 K and 5.6 mW, respectively. |
| doi_str_mv | 10.1109/TVLSI.2011.2170203 |
| format | Article |
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To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP) is employed to accelerate the speed of feature matching. The VVP can transform hundreds of 128-D SIFT vectors into a 64-D histogram for object matching by using the binary-tree-based architecture, and 16 calculators for the computations of the Euclidean distances are designed for each of the two processors in each level. A total of 126 visual words can be saved in the six-level hierarchical memory, which instantly offers the data required for the matching process, and more than 5 times of bandwidth can be saved compared with the non-binary-tree-based architecture. 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Solid state devices ; System-on-a-chip ; system-on-a-chip (SoC) ; Visualization</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2012-12, Vol.20 (12), p.2329-2332</ispartof><rights>2014 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c297t-678119018d132f76bd3590162c59eefba45d6e5b7376a89d7feedbfca34b1dc83</citedby><cites>FETCH-LOGICAL-c297t-678119018d132f76bd3590162c59eefba45d6e5b7376a89d7feedbfca34b1dc83</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6062665$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6062665$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=26737098$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>CHEN, Tse-Wei</creatorcontrib><creatorcontrib>SU, Yu-Chi</creatorcontrib><creatorcontrib>HUANG, Keng-Yen</creatorcontrib><creatorcontrib>TSAI, Yi-Min</creatorcontrib><creatorcontrib>CHIEN, Shao-Yi</creatorcontrib><creatorcontrib>CHEN, Liang-Gee</creatorcontrib><title>Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Feature matching is an indispensable process for object recognition, which is an important issue for wearable devices with video analysis functionalities. To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP) is employed to accelerate the speed of feature matching. The VVP can transform hundreds of 128-D SIFT vectors into a 64-D histogram for object matching by using the binary-tree-based architecture, and 16 calculators for the computations of the Euclidean distances are designed for each of the two processors in each level. A total of 126 visual words can be saved in the six-level hierarchical memory, which instantly offers the data required for the matching process, and more than 5 times of bandwidth can be saved compared with the non-binary-tree-based architecture. As a part of the recognition SoC, the VVP is implemented with the 65-nm CMOS technology, and the experimental results show that the gate count and the average power consumption are 280 K and 5.6 mW, respectively.</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Computer architecture</subject><subject>Computer vision</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>digital circuit</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>hardware architecture</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Object recognition</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>System-on-a-chip</subject><subject>system-on-a-chip (SoC)</subject><subject>Visualization</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9UE1PwzAMrRBIjMEfgEsuHDvysSbNcQPGJk0agrJrlaYOZMraKWkP_HtSNs0X289-z_JLknuCJ4Rg-VRs15-rCcWETCgRmGJ2kYxIlolUxriMNeYszSnB18lNCDuMyXQq8Sjptjb0yqFtq1XVO-V_0btvNYTQejRXAWrUNmhum2FSeAA08_rHdqC73gMycesDlEsLuwe0qXYRj4Buvxvb2ci0DVr0zqXLlwiH1vUDeptcGeUC3J3yOPlavBbPy3S9eVs9z9applJ0KRc5IRKTvCaMGsGrmmWx5VRnEsBUaprVHLJKMMFVLmthAOrKaMWmFal1zsYJPepq34bgwZQHb_fxk5LgcvCt_PetHHwrT75F0uORdFBBK2e8arQNZybl8RyWg_jDcc8CwHnMMaecZ-wPAS54Ng</recordid><startdate>20121201</startdate><enddate>20121201</enddate><creator>CHEN, Tse-Wei</creator><creator>SU, Yu-Chi</creator><creator>HUANG, Keng-Yen</creator><creator>TSAI, Yi-Min</creator><creator>CHIEN, Shao-Yi</creator><creator>CHEN, Liang-Gee</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20121201</creationdate><title>Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution</title><author>CHEN, Tse-Wei ; SU, Yu-Chi ; HUANG, Keng-Yen ; TSAI, Yi-Min ; CHIEN, Shao-Yi ; CHEN, Liang-Gee</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c297t-678119018d132f76bd3590162c59eefba45d6e5b7376a89d7feedbfca34b1dc83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Computer architecture</topic><topic>Computer vision</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>digital circuit</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>hardware architecture</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Object recognition</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>System-on-a-chip</topic><topic>system-on-a-chip (SoC)</topic><topic>Visualization</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>CHEN, Tse-Wei</creatorcontrib><creatorcontrib>SU, Yu-Chi</creatorcontrib><creatorcontrib>HUANG, Keng-Yen</creatorcontrib><creatorcontrib>TSAI, Yi-Min</creatorcontrib><creatorcontrib>CHIEN, Shao-Yi</creatorcontrib><creatorcontrib>CHEN, Liang-Gee</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN, Tse-Wei</au><au>SU, Yu-Chi</au><au>HUANG, Keng-Yen</au><au>TSAI, Yi-Min</au><au>CHIEN, Shao-Yi</au><au>CHEN, Liang-Gee</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2012-12-01</date><risdate>2012</risdate><volume>20</volume><issue>12</issue><spage>2329</spage><epage>2332</epage><pages>2329-2332</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Feature matching is an indispensable process for object recognition, which is an important issue for wearable devices with video analysis functionalities. To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP) is employed to accelerate the speed of feature matching. The VVP can transform hundreds of 128-D SIFT vectors into a 64-D histogram for object matching by using the binary-tree-based architecture, and 16 calculators for the computations of the Euclidean distances are designed for each of the two processors in each level. A total of 126 visual words can be saved in the six-level hierarchical memory, which instantly offers the data required for the matching process, and more than 5 times of bandwidth can be saved compared with the non-binary-tree-based architecture. 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| subjects | Applied sciences Circuit properties Computer architecture Computer vision Design. Technologies. Operation analysis. Testing digital circuit Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology hardware architecture Integrated circuits Integrated circuits by function (including memories and processors) Object recognition Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices System-on-a-chip system-on-a-chip (SoC) Visualization |
| title | Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution |
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