A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	I-Ning Ku, Zhiwei Xu, Yen-Cheng Kuan, Yen-Hsiang Wang, Chang, M.-C F.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arrays Calibration Capacitors Clocks CMOS integrated circuits Resistors Timing
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