A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS
A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 4 |
|---|---|
| container_issue | |
| container_start_page | 1 |
| container_title | |
| container_volume | |
| creator | I-Ning Ku Zhiwei Xu Yen-Cheng Kuan Yen-Hsiang Wang Chang, M.-C F. |
| description | A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate mismatches within channels. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm 2 chip area and consumes 40 mW at 2.2 GS/s from a 1 V supply. Measured SNDR and SFDR are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. |
| doi_str_mv | 10.1109/CICC.2011.6055328 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6055328</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6055328</ieee_id><sourcerecordid>6055328</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-1dda7f32b5ec0a6ff6840aff722f28a1996771a40f96cbba36b2d3e077d9c1313</originalsourceid><addsrcrecordid>eNo1kMlOwzAYhM0m0ZY-AOLiF3D6246XHKsApVJRDwVxrJzEjoyyVHZKxNtTRLnMHEbfaDQI3VNIKIVska_zPGFAaSJBCM70BZrSVCgFjFFxiSYnZYRLDldonin9nzF9jSagtSQi43CLpjF-AtAs02yCwhKnQNoPrEjhB8wSRla7RcSDby3x3WBDY82XrXA8FsF0te9qvHzMsesDbvqRHPrRBlz72vziow-2sTHism_bY-dLM_i-i9h3WArStTh_3e7u0I0zTbTzs8_Q-_PTW_5CNtvVOl9uiKdKDIRWlVGOs0LYEox0TuoUjHOKMce0Oe2XSlGTgstkWRSGy4JV3IJSVVZSTvkMPfz1emvt_hB8a8L3_vwd_wH89FzG</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>I-Ning Ku ; Zhiwei Xu ; Yen-Cheng Kuan ; Yen-Hsiang Wang ; Chang, M.-C F.</creator><creatorcontrib>I-Ning Ku ; Zhiwei Xu ; Yen-Cheng Kuan ; Yen-Hsiang Wang ; Chang, M.-C F.</creatorcontrib><description>A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate mismatches within channels. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm 2 chip area and consumes 40 mW at 2.2 GS/s from a 1 V supply. Measured SNDR and SFDR are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate.</description><identifier>ISSN: 0886-5930</identifier><identifier>ISBN: 9781457702228</identifier><identifier>ISBN: 1457702223</identifier><identifier>EISSN: 2152-3630</identifier><identifier>EISBN: 1457702215</identifier><identifier>EISBN: 9781457702235</identifier><identifier>EISBN: 1457702231</identifier><identifier>EISBN: 9781457702211</identifier><identifier>DOI: 10.1109/CICC.2011.6055328</identifier><language>eng</language><publisher>IEEE</publisher><subject>Arrays ; Calibration ; Capacitors ; Clocks ; CMOS integrated circuits ; Resistors ; Timing</subject><ispartof>2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6055328$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6055328$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>I-Ning Ku</creatorcontrib><creatorcontrib>Zhiwei Xu</creatorcontrib><creatorcontrib>Yen-Cheng Kuan</creatorcontrib><creatorcontrib>Yen-Hsiang Wang</creatorcontrib><creatorcontrib>Chang, M.-C F.</creatorcontrib><title>A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS</title><title>2011 IEEE Custom Integrated Circuits Conference (CICC)</title><addtitle>CICC</addtitle><description>A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate mismatches within channels. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm 2 chip area and consumes 40 mW at 2.2 GS/s from a 1 V supply. Measured SNDR and SFDR are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate.</description><subject>Arrays</subject><subject>Calibration</subject><subject>Capacitors</subject><subject>Clocks</subject><subject>CMOS integrated circuits</subject><subject>Resistors</subject><subject>Timing</subject><issn>0886-5930</issn><issn>2152-3630</issn><isbn>9781457702228</isbn><isbn>1457702223</isbn><isbn>1457702215</isbn><isbn>9781457702235</isbn><isbn>1457702231</isbn><isbn>9781457702211</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kMlOwzAYhM0m0ZY-AOLiF3D6246XHKsApVJRDwVxrJzEjoyyVHZKxNtTRLnMHEbfaDQI3VNIKIVska_zPGFAaSJBCM70BZrSVCgFjFFxiSYnZYRLDldonin9nzF9jSagtSQi43CLpjF-AtAs02yCwhKnQNoPrEjhB8wSRla7RcSDby3x3WBDY82XrXA8FsF0te9qvHzMsesDbvqRHPrRBlz72vziow-2sTHism_bY-dLM_i-i9h3WArStTh_3e7u0I0zTbTzs8_Q-_PTW_5CNtvVOl9uiKdKDIRWlVGOs0LYEox0TuoUjHOKMce0Oe2XSlGTgstkWRSGy4JV3IJSVVZSTvkMPfz1emvt_hB8a8L3_vwd_wH89FzG</recordid><startdate>201109</startdate><enddate>201109</enddate><creator>I-Ning Ku</creator><creator>Zhiwei Xu</creator><creator>Yen-Cheng Kuan</creator><creator>Yen-Hsiang Wang</creator><creator>Chang, M.-C F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201109</creationdate><title>A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS</title><author>I-Ning Ku ; Zhiwei Xu ; Yen-Cheng Kuan ; Yen-Hsiang Wang ; Chang, M.-C F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-1dda7f32b5ec0a6ff6840aff722f28a1996771a40f96cbba36b2d3e077d9c1313</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Arrays</topic><topic>Calibration</topic><topic>Capacitors</topic><topic>Clocks</topic><topic>CMOS integrated circuits</topic><topic>Resistors</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>I-Ning Ku</creatorcontrib><creatorcontrib>Zhiwei Xu</creatorcontrib><creatorcontrib>Yen-Cheng Kuan</creatorcontrib><creatorcontrib>Yen-Hsiang Wang</creatorcontrib><creatorcontrib>Chang, M.-C F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>I-Ning Ku</au><au>Zhiwei Xu</au><au>Yen-Cheng Kuan</au><au>Yen-Hsiang Wang</au><au>Chang, M.-C F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS</atitle><btitle>2011 IEEE Custom Integrated Circuits Conference (CICC)</btitle><stitle>CICC</stitle><date>2011-09</date><risdate>2011</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>0886-5930</issn><eissn>2152-3630</eissn><isbn>9781457702228</isbn><isbn>1457702223</isbn><eisbn>1457702215</eisbn><eisbn>9781457702235</eisbn><eisbn>1457702231</eisbn><eisbn>9781457702211</eisbn><abstract>A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate mismatches within channels. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm 2 chip area and consumes 40 mW at 2.2 GS/s from a 1 V supply. Measured SNDR and SFDR are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate.</abstract><pub>IEEE</pub><doi>10.1109/CICC.2011.6055328</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0886-5930 |
| ispartof | 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4 |
| issn | 0886-5930 2152-3630 |
| language | eng |
| recordid | cdi_ieee_primary_6055328 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Arrays Calibration Capacitors Clocks CMOS integrated circuits Resistors Timing |
| title | A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T01%3A57%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%2040-mW%207-bit%202.2-GS/s%20time-interleaved%20subranging%20ADC%20for%20low-power%20gigabit%20wireless%20communications%20in%2065-nm%20CMOS&rft.btitle=2011%20IEEE%20Custom%20Integrated%20Circuits%20Conference%20(CICC)&rft.au=I-Ning%20Ku&rft.date=2011-09&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.issn=0886-5930&rft.eissn=2152-3630&rft.isbn=9781457702228&rft.isbn_list=1457702223&rft_id=info:doi/10.1109/CICC.2011.6055328&rft_dat=%3Cieee_6IE%3E6055328%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1457702215&rft.eisbn_list=9781457702235&rft.eisbn_list=1457702231&rft.eisbn_list=9781457702211&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6055328&rfr_iscdi=true |