Implementation of Sigma-Delta Analog to Digital Converter in FPGA

Implementation of Sigma-Delta Analog to Digital Converter in FPGA

This paper presents implementation of a second-order Sigma-Delta Analog to Digital Converter (ADC) for audio band in field-programmable gate array (FPGA) Xilinx Virtex5. This family of FPGA contains a differential input buffers, which are used to create a continuous-time integrators as a loop filter...

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Bibliographische Detailangaben
Hauptverfasser: Mihalov, J., Stopjakova, V.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitors
Clocks
Field programmable gate arrays
Noise
Resistors
Sigma delta modulation
Signal resolution
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Beschreibung
Zusammenfassung:This paper presents implementation of a second-order Sigma-Delta Analog to Digital Converter (ADC) for audio band in field-programmable gate array (FPGA) Xilinx Virtex5. This family of FPGA contains a differential input buffers, which are used to create a continuous-time integrators as a loop filter stages. The implementation is done using hardware description language (VHDL).
ISSN:1803-7232