A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS

A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS

This paper presents a 0.48-mW/Gbps optical receiver in a 65-nm CMOS process. The receiver includes a tran-simpedance amplifier (TIA) with a DC offset canceler (DCOC) combined with an autothreshold controller (ATC) function for providing low-power, area-efficient single-ended-to-differential conversi...

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Hauptverfasser: Akita, I., Tsubouchi, Y., Itakura, T., Nishigaki, M., Uemura, H., Furuyama, H., Shibata, H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bit error rate
CMOS integrated circuits
Optical buffering
Optical receivers
Optical sensors
Optical variables measurement
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Zusammenfassung:This paper presents a 0.48-mW/Gbps optical receiver in a 65-nm CMOS process. The receiver includes a tran-simpedance amplifier (TIA) with a DC offset canceler (DCOC) combined with an autothreshold controller (ATC) function for providing low-power, area-efficient single-ended-to-differential conversion. The fabricated 6-Gbps optical receiver consumes 2.86-mW power and achieves less than -3.8-dBm sensitivity at a BER of 10 -11 .
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2011.6044977